3D Memory Channel Doping Through Bottom Conductor Opening
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Solution Overview
Problem
Current 3D memory device fabrication methods face challenges in optimizing performance and functionality due to processing steps that can introduce inefficiencies and limitations in achieving higher storage density, lower power consumption, and better cost efficiency.
Innovation Solution
A semiconductor device fabrication method involving a processing wafer with a core region and a staircase structure, where a channel hole extends vertically through conductor/dielectric tiers, with specific patterning, etching, impurity implantation, and laser activation steps to optimize the structure and performance of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used for 3D memory devices, then the manufacturing process is simpler, but the storage density and performance are insufficient
Solution Approach 1:
The fabrication process is divided into distinct stages: forming conductor/dielectric tiers with conductor layers, creating channel holes through etching, depositing memory films on channel hole sidewalls, and forming select gates. This segmentation allows each component to be optimized independently while achieving high storage density through vertical stacking of multiple tiers.
Solution Approach 2:
The patent transitions from planar 2D memory architecture to 3D vertical architecture by stacking multiple conductor/dielectric tiers vertically and forming channel holes that extend through multiple tiers. This dimensional change enables significantly higher storage density by utilizing the vertical space rather than expanding horizontally.
2Manufacturing precision
If processing steps are added to improve performance, then storage density increases, but power consumption increases
Solution Approach 1:
The patent implements local quality by forming select gates only in specific regions (first and second select gate regions) rather than uniformly across the entire device. The control gates are also positioned locally adjacent to specific memory cells. This localized approach reduces overall power consumption while maintaining high storage density in the active regions.
Solution Approach 2:
The patent employs dynamic control through select gates that can be independently activated to enable or disable specific memory cell strings. This dynamic switching capability allows the device to operate with lower power by activating only the necessary memory cells rather than maintaining all cells in an active state.
3Reliability
If conventional fabrication methods are used, then manufacturing cost is lower, but performance and efficiency are insufficient
Solution Approach 1:
The conductor layers serve multiple functions: they act as control gates for memory cells, form select gates for string selection, and provide electrical connectivity between different tiers. The channel holes serve dual purposes as both structural elements and pathways for charge storage. This multi-functionality reduces the need for separate dedicated structures, improving performance while managing manufacturing complexity.
Solution Approach 2:
The patent performs preliminary actions by forming the conductor/dielectric tiers and channel holes before depositing the memory films. The control gates are positioned adjacent to memory cells during the tier formation stage. This preliminary structuring simplifies subsequent steps and improves overall manufacturing efficiency despite the complex final structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the performance and efficiency of 3D memory devices by improving impurity implantation and reducing the complexity of the fabrication process, leading to better storage density, lower power consumption, and cost efficiency.
Implementation Method 1
performing laser activation on the processing wafer
Implementation Method 2
performing impurity implantation on the processing wafer
Data Source
AI summary
A semiconductor device fabrication method includes providing a processing wafer. The processing wafer has core and staircase structure (SS) regions, and includes a bottom conductor layer, conductor/dielectric tier(s) over the bottom conductor layer, and a channel hole (CH) in the core region and extending approximately vertically through the conductor/dielectric tier(s). The CH includes a channel layer and a memory film surrounding the channel layer. A protrusion portion of the channel layer and a protrusion portion of the memory film extend into the bottom conductor layer. The method further includes patterning the bottom conductor layer to remove a portion of the bottom conductor layer in the core region to expose the protrusion portion of the memory film, performing etching to remove the protrusion portion of the memory film to expose the protrusion portion of the channel layer, performing impurity implantation, and performing laser activation.