Bottom Dielectric Isolation Layer for Uniform Backside S/D Contacts
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced feature sizes, challenges arise in achieving uniformity and precision in the formation of source/drain regions and contact plugs, leading to non-uniformity and complexity in manufacturing processes.
Innovation Solution
The implementation of a bottom dielectric isolation layer as an etch stop layer during the formation of source/drain recesses, combined with self-aligned backside contact openings, ensures uniformity and precision by using the same planar semiconductor sacrificial layer throughout the wafer, allowing for the formation of self-aligned backside contact plugs and improved depth uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional etching processes are used for source/drain recess formation, then manufacturing process complexity increases, but manufacturing precision deteriorates due to non-uniformity
Solution Approach 1:
A bottom dielectric isolation layer is formed prior to source/drain recess etching to establish a uniform etch stop plane across the wafer. This preliminary structure enables subsequent etching processes to achieve consistent depth and uniformity without requiring complex process control, directly resolving the contradiction between manufacturing precision and process complexity
Solution Approach 2:
The bottom dielectric isolation layer acts as an intermediary etch stop layer between the source/drain regions and the substrate. This intermediate structure provides a well-defined stopping point for etching processes, ensuring uniform recess formation while simplifying the overall manufacturing process by eliminating the need for multiple etch steps with different parameters
2Quantity of substance
If feature sizes are reduced to increase integration density, then integration density improves, but manufacturing precision deteriorates due to difficulty in achieving uniformity
Solution Approach 1:
The bottom dielectric isolation layer is formed in advance to create a uniform reference plane before patterning and etching at reduced feature sizes. This preliminary structure ensures that even as feature dimensions shrink, the etching process maintains consistent depth and uniformity across the wafer, enabling high integration density without sacrificing manufacturing precision
Solution Approach 2:
The introduction of the bottom dielectric isolation layer changes the etching parameter landscape by providing a well-defined etch stop at a specific depth. This parameter change allows for precise control of source/drain recess depth even when lateral feature sizes are reduced, thereby maintaining manufacturing precision while enabling higher integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity and precision of source/drain regions and contact plugs, improving manufacturing efficiency and reducing complexity by ensuring consistent depth and alignment across the wafer.
Implementation Method 1
The bottom dielectric isolation layer is used as an etch stop layer in the formation of source/drain recesses
Implementation Method 2
The bottom dielectric isolation layer may also be implanted, so that the implanted portions may be used as self-aligned features
Data Source
AI summary
A method includes forming a wafer comprising a substrate, a sacrificial layer over the substrate, and a multilayer stack over the sacrificial layer. The method further includes performing a first etching process on the multilayer stack and the sacrificial layer to form a patterned multilayer stack, replacing a part of the sacrificial layer in the patterned multilayer stack with a bottom dielectric isolation layer, performing a second etching process on the patterned multilayer stack to form a source/drain recess, wherein a surface of the bottom dielectric isolation layer is exposed to the source/drain recess, and forming a lower source/drain region and an upper source/drain region in the source/drain recess. The substrate is removed to reveal the bottom dielectric isolation layer. A portion of the bottom dielectric isolation layer is removed to form a backside contact opening. A a source/drain silicide layer is formed in the backside contact opening.