Bottom Fin Trim Isolation for Stacked Device Architectures
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Solution Overview
Problem
Stacked semiconductor fin structures face challenges in electrical isolation, where isolating regions on the bottom fin often requires corresponding electrical separation of the top fin, which is not always feasible or practical, affecting the density and performance of integrated circuits.
Innovation Solution
The method involves selectively etching or oxidizing the bottom semiconductor fin to create an insulating region without cutting or isolating the top fin, using techniques like selective wet etching or oxidation catalysts like aluminum oxide to form an insulating oxide, allowing for CMOS routing and fin trim isolation on the bottom device layer only.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical isolation is implemented on the bottom fin by cutting or separating regions, then electrical isolation between regions is achieved, but the top fin must also be correspondingly separated which reduces device density and complicates the structure
Solution Approach 1:
The patent segments the isolation function between two distinct structures: a through-isolation structure extending from the top surface to the bottom surface, and a bottom fin trim isolation structure extending from the bottom surface into the bottom fin. This segmentation allows the bottom fin to be electrically isolated without requiring corresponding separation of the top fin, resolving the contradiction between achieving electrical isolation and maintaining structural simplicity.
Solution Approach 2:
The patent introduces a vertical dimension solution by creating isolation structures that extend through the substrate thickness, isolating the bottom fin regions vertically without affecting the horizontal continuity of the top fin. This dimensional approach enables independent isolation control of the bottom fin while preserving the top fin integrity.
2Reliability
If the top fin is cut or separated to achieve isolation, then electrical isolation is achieved, but device density decreases due to loss of active fin material
Solution Approach 1:
The patent extracts the isolation function from the top fin structure and relocates it to dedicated isolation structures formed at the bottom fin level. The bottom fin trim isolation structure is formed by removing material specifically from the bottom fin region and filling with insulating material, thereby achieving isolation without removing or separating the top fin active material that contributes to device density.
Solution Approach 2:
The patent applies local quality by creating isolation structures with specific spatial characteristics: the bottom fin trim isolation structure is positioned locally at the bottom fin regions requiring isolation, extending from the bottom surface upward into the bottom fin but stopping before affecting the top fin. This localized approach achieves necessary isolation while preserving the continuity and integrity of the top fin for maximum device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of vertically stacked CMOS transistors with self-aligned electrical isolation, increasing the density of integrated circuits without compromising the integrity of the top fin structure, facilitating efficient CMOS routing and improving performance.
Implementation Method 1
using techniques like selective wet etching or oxidation catalysts like aluminum oxide to form an insulating oxide
Implementation Method 2
an insulator region extending horizontally in the length direction and to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin
Data Source
AI summary
An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.