Bottom-Gate Channel Layout for Dense Semiconductor Interconnects
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Solution Overview
Problem
There is a growing demand for semiconductor devices with high reliability and integration density, which existing technologies have not adequately addressed in terms of structural complexity and performance.
Innovation Solution
A semiconductor device design featuring a channel region between source/drain patterns with a gate electrode on the bottom surface and an upper interconnection line on the insulating layer, along with specific configurations of source/drain patterns and active regions, to enhance connectivity and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel region is disposed between source/drain patterns with a gate electrode on the bottom surface, then the integration density is improved, but the structural complexity increases
Solution Approach 1:
The gate electrode is positioned on the bottom surface of the active pattern rather than the top surface, utilizing the vertical dimension to achieve higher integration density while maintaining manageable structural complexity through standardized topological relationships
Solution Approach 2:
The source/drain patterns are divided into first and second portions with different widths, creating segmented structures that optimize both connectivity and structural organization, allowing the channel region to be properly positioned between them
2Ease of operation
If the upper interconnection line is disposed on the top surface of the active pattern, then the connectivity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The insulating layer is formed on the top surface of the active pattern before the upper interconnection line is disposed, creating a pre-prepared interface that facilitates accurate alignment and connection while maintaining ease of connectivity
Solution Approach 2:
The insulating layer serves as an intermediary between the active pattern and the upper interconnection line, providing a controlled interface that reduces manufacturing precision requirements while ensuring proper electrical isolation and connectivity
Data Source
AI summary
A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.