Bottom Gate LTPS TFT Array Substrate Manufacturing
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Solution Overview
Problem
The traditional top gate structure in low-temperature polysilicon thin-film transistors (LTPS TFTs) results in a non-smooth active layer surface, leading to uneven interface resistance and instability in the overall performance due to poor flatness and incomplete filling of source and drain lines, which can cause air bubbles and poor contact.
Innovation Solution
A manufacturing method for an array substrate with a bottom gate structure, involving the formation of a gate layer, gate insulating layer, polysilicon material layer, etch stop layer, and source/drain layers, where the etch stop layer prevents surface irregularities and ensures proper contact between the source, drain, and active layer, reducing the risk of air bubbles and uneven filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a top gate structure is used in LTPS TFTs, then the transistor can be manufactured with conventional processes, but the active layer surface becomes non-smooth leading to uneven interface resistance and poor performance stability
Solution Approach 1:
The patent inverts the traditional top gate structure to a bottom gate structure. The gate layer is positioned beneath the active layer instead of above it, which fundamentally changes the interface characteristics. This inversion eliminates the surface roughness problem caused by depositing gate material over the active layer, as the gate now serves as the base layer upon which the active layer is formed, ensuring a smooth interface and uniform resistance distribution.
Solution Approach 2:
The patent introduces a multi-layer stacked structure with vertical dimensionality, consisting of substrate, gate layer, gate insulating layer, active layer, and source/drain layers in sequential stacking. This dimensional arrangement separates the gate function from the active layer surface, allowing the active layer to be deposited on a smooth gate insulating surface rather than having the gate deposited on top of it, thus resolving the interface roughness issue.
2Ease of manufacture
If the active layer surface is non-smooth, then deposition can proceed, but the flatness of subsequently deposited gate structures deteriorates and interface resistance becomes uneven
Solution Approach 1:
The patent performs preliminary action by forming the gate layer and gate insulating layer before depositing the active layer. The gate insulating layer is deposited and planarized in advance, providing a smooth baseline surface. This preliminary preparation ensures that when the active layer is subsequently deposited, it forms on a uniform surface, guaranteeing both good flatness and uniform interface resistance without requiring post-deposition surface treatment.
3Ease of manufacture
If traditional filling methods are used for source and drain lines, then the structure can be completed, but incomplete filling and air bubbles occur leading to poor contact
Solution Approach 1:
The patent introduces an etch stop layer as an intermediary between the active layer and the source/drain lines. This etch stop layer serves as a mediator that facilitates complete filling of the source and drain regions. The etch stop layer provides a distinct interface that enables precise etching and filling control, preventing air bubble entrapment and ensuring complete material filling, thereby guaranteeing reliable electrical contact between source/drain lines and the active layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bottom gate structure reduces uneven interface resistance, enhances the stability of electrical properties, and improves the contact between the source, drain, and active layer, preventing incomplete filling and air bubbles, thus stabilizing the overall performance of the thin film transistor.
Implementation Method 1
channel doping the polysilicon material layer
Implementation Method 2
depositing an etch stop material layer on the polysilicon material layer
Data Source
AI summary
The present disclosure provides a manufacturing method of an array substrate, including: forming a gate layer on a substrate; forming a gate insulating material layer on the gate layer; forming a polysilicon material layer on the gate insulating material layer; depositing an etch stop material layer on the polysilicon material layer; channel doping the polysilicon material layer; etching the polysilicon material layer, the etch stop material layer and the gate insulating material layer to form an active layer, an etch stop layer and a gate insulating layer; forming a source/drain layer on the active layer and the gate insulating layer, the active layer being electrically connected to the source/drain layer; and forming a through hole on the source/drain layer to form a source and a drain, the through hole being corresponding to the active layer, and both of the source and the drain being electrically connected to the active layer.