Bottom Gate Thin Film Transistor Hard Mask Etching
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Solution Overview
Problem
Bottom gate channel etched thin film transistors using oxide semiconductors for liquid crystal display devices face issues with initial threshold voltage depletion and shift due to side etching and oxygen deficiency during dry etching processes, leading to performance inconsistencies and reliability concerns.
Innovation Solution
A bottom gate channel etched thin film transistor design incorporating a hard mask layer of inorganic compounds, such as silicon oxide, silicon nitride, or silicon oxynitride, to prevent side etching and oxygen deficiency, with a protective insulating film covering the source and drain electrode interconnections to maintain oxide semiconductor integrity, and using chlorine gas for dry etching while minimizing exposure to carbon and hydrogen.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dry etching with chlorine gas is used to pattern Al interconnection material for source and drain electrodes, then low sheet resistance and high conductivity are achieved, but side etching occurs on processed side walls causing threshold voltage depletion and shift
Solution Approach 1:
A side wall protective film made of carbon material is introduced as an intermediary layer between the Al interconnection material and the etching environment. This protective film prevents chlorine gas from directly attacking the Al side walls, eliminating side etching and the associated threshold voltage depletion and shift while allowing the Al material to maintain its low sheet resistance and high conductivity
Solution Approach 2:
The side wall protective film is formed in advance before the dry etching process to preemptively protect the Al interconnection material from side etching. By establishing this protective barrier beforehand, the patent prevents the harmful side etching effect from occurring during the etching process, thereby maintaining threshold voltage stability
2Reliability
If oxide semiconductor layer is used for channel layer to achieve high mobility, then transistor performance is improved, but the oxide semiconductor is easily etched with acid solution causing manufacturing complexity
Solution Approach 1:
The patent changes the etching parameter from acid solution to chlorine gas-based dry etching. This parameter change allows the oxide semiconductor layer to be patterned without being easily etched away, as the dry etching process with chlorine gas provides selective etching that maintains the integrity of the oxide semiconductor while enabling precise patterning for high-performance transistors
3Area of stationary object
If source and drain electrode interconnection width is decreased to improve aperture ratio, then display resolution is enhanced, but parasitic capacitance control becomes more difficult
Solution Approach 1:
The patent uses chlorine gas for dry etching the Al interconnection material, which provides precise etching control and clean profiles. This allows the source and drain electrode interconnections to be narrowed to improve aperture ratio while maintaining well-controlled parasitic capacitance through the precision and cleanliness of the dry etching process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses initial threshold voltage depletion and shift, ensuring stable transistor performance and improved reliability by reducing side etching and oxygen deficiency, thus enhancing the aperture ratio and reducing parasitic capacitance in high-definition display devices.
Implementation Method 1
dry etching the Al-based metal film using the first hard mask layer and the second hard mask layer for masks with a chlorine gas
Implementation Method 2
removing a residual chlorine gas component by a plasma process
Data Source
AI summary
There is provided a bottom gate channel etched thin film transistor that can suppress initial Vth depletion and a Vth shift. A thin film transistor is formed, including a gate electrode interconnection disposed on a substrate, a gate insulating film, an oxide semiconductor layer to be a channel layer, a stacked film of a source electrode interconnection and a first hard mask layer, a stacked film of a drain electrode interconnection and a second hard mask layer, and a protective insulating film.