Patterned Bottom-Gate Oxide TFTs to Prevent Sidewall Redeposition
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Solution Overview
Problem
The fabrication of semiconducting metal oxide thin-film transistors (TFTs) faces challenges due to sidewall re-deposition of metallic materials during the patterning process, leading to leakage paths between the bottom gate and source/drain regions, which reduces the reliability of the TFT devices.
Innovation Solution
The solution involves patterning the bottom gates of TFTs to prevent sidewall re-deposition by embedding them in a dielectric layer, ensuring the top surface of the patterned bottom gates is co-planar with the dielectric layer, and using AlOx/IGZO/AlOx materials to cover the gates during etching, thereby controlling the dimension and overlay of the bottom gates and source/drain regions precisely.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional patterning process is used, then manufacturing process is simple, but sidewall re-deposition occurs causing leakage paths and reducing device reliability
Solution Approach 1:
A protective layer is formed over the bottom gate electrode before the patterning process. This preliminary protective action prevents metallic material from re-depositing on the bottom gate sidewalls during subsequent etching operations, thereby eliminating leakage paths and improving device reliability without complicating the manufacturing process
Solution Approach 2:
The protective layer acts as an intermediary barrier between the metallic materials being patterned and the bottom gate electrode. This intermediary layer prevents direct contact and re-deposition of metals on the gate sidewalls, solving the harmful re-deposition effect while maintaining process simplicity
2Reliability
If higher temperatures are used for dopant activation, then dopant activation is more effective, but low-k dielectric materials decompose thermally
Solution Approach 1:
The patent employs low-temperature dopant activation techniques, changing the temperature parameter from conventional high temperatures to below 400°C. This parameter change enables effective dopant activation while preventing thermal decomposition of low-k dielectric materials, resolving the contradiction between activation effectiveness and material stability
3Ease of manufacture
If bottom gates are not patterned, then manufacturing process is simpler, but metallic re-deposition cannot be prevented
Solution Approach 1:
The bottom gate electrode is patterned before forming the protective layer and subsequent structures. This preliminary patterning action defines the gate dimensions and position, enabling precise control of device geometry while the subsequently formed protective layer prevents re-deposition, achieving both manufacturing ease and prevention of harmful effects
Data Source
AI summary
A semiconductor device includes a first dielectric layer, a gate electrode embedded within the first dielectric layer, a layer stack including a gate dielectric layer, a channel layer including a semiconducting metal oxide material, and a second dielectric layer, and a source electrode and a drain electrode embedded in the second dielectric layer and contacting a respective portion of a top surface of the channel layer. A combination of the gate electrode, the gate dielectric layer, the channel layer, the source electrode, and the drain electrode forms a transistor. The total length of the periphery of a bottom surface of the channel layer that overlies the gate electrode is equal to the width of the gate electrode or twice the width of the gate electrode, and resputtering of the gate electrode material on sidewalls of the channel layer is minimized.