Bottom-Gate TFT Contact Hole Layout for Light Shielding Stability

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Solution Overview

Problem

Bottom-gate type thin film transistors in display devices face challenges in light shielding and stability due to limited shielding effect and potential breakage at the edge of the gate, leading to photogenerated leakage currents and reduced bonding yield.

Innovation Solution

The design includes a display panel with a thin film transistor structure where the gate's orthographic projection covers at least part of the contact holes on the substrate, increasing the shielding range and ensuring that contact holes are not located at the step edge, thereby improving light shielding and bonding stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a bottom-gate type transistor is used, then the mask and cost are saved, but the shielding effect on backside light is limited and stability is reduced

Engineering Contradiction:
Improvemask and costVSAvoidstability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The gate structure is extended in the vertical dimension to overlap with contact holes, transforming a two-dimensional planar gate into a three-dimensional structure that provides shielding in the depth direction, thereby improving light blocking capability without changing the bottom-gate configuration

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The gate structure serves as an intermediary element that simultaneously performs electrical control and optical shielding functions by positioning it to overlap with contact holes, where it blocks light from reaching the active layer through the contact hole regions

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If the gate is positioned to cover contact holes, then light shielding is improved, but the device complexity increases

Engineering Contradiction:
Improvelight shielding effectVSAvoiddevice complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The gate structure is designed to perform multiple functions simultaneously: electrical control of the transistor and optical shielding of contact holes. This multi-functionality approach improves light shielding without adding separate shielding structures, thereby avoiding increased device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The shielding function is merged with the gate structure itself rather than being implemented as a separate component. By combining the electrical control function and optical shielding function into a single gate structure, the design achieves improved light blocking without increasing overall device complexity

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces photogenerated leakage currents, enhances bonding yield, and improves signal transmission stability, leading to better display performance and reduced crosstalk in display panels.

Implementation Method 1

the shielding effect of the bottom gate on backside light of the active layer is limited

Methodology Applied
Scientific EffectLight absorption: Absorption (EM radiation)

Implementation Method 2

improve the shielding effect of a first gate and a second gate on light

Methodology Applied
Scientific EffectLight reflection: Reflection

Data Source

PatentUS20240094587A1Display panel and display device
Publication Date: 2024.03.21 WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
  • US20240094587A1 patent drawing
  • US20240094587A1 patent drawing
  • US20240094587A1 patent drawing

AI summary

The present disclosure provides a display panel and a display device. The display panel includes a thin film transistor; and further includes a substrate,; a first metal layer disposed on the substrate and including a gate of the thin film transistor; an active layer disposed on a side of the first metal layer away from the substrate and including an active portion of the thin film transistor; a spacer layer disposed on a side of the active layer away from the first metal layer and including a plurality of contact holes; a second metal layer disposed on a side of the spacer layer away from the active layer and including a source and a drain of the thin film transistor; an orthographic projection of the gate electrode on the substrate covers an orthographic projection of at least part of the contact holes on the substrate.