Bottom-Gate Thin-Body Transistors for 3D Stacked ICs
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Solution Overview
Problem
Current stacked transistor configurations for integrated circuits, such as those used in imaging systems, face challenges including restricted metal line routing, thermal cycle-induced degradation of photodiodes, high fabrication costs, and poor wafer-to-wafer interconnect density, which hinder the development of low-cost, high-performance, and low-power 3D stacking solutions.
Innovation Solution
The implementation of bottom-gate thin-body dual-oxide dual-voltage transistors, which involve forming transistors with a gate conductor over a channel region, using salicide to reduce resistance, and employing shallow and deep trench isolation structures to optimize transistor performance and density, allowing for monolithic stacking and reduced need for multiple wafers with separate routing layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SOI pixel transistors are formed above photodiodes in a stacked configuration, then 3D logic integration is enabled, but metal line routing is restricted and thermal cycles degrade photodiode doping
Solution Approach 1:
The patent transitions from planar transistor-gate configurations to a vertical bottom-gate architecture where the gate extends underneath the channel region. This dimensional change allows metal line routing to occur in the lateral plane without being constrained by overhead gate structures, thereby enabling complex interconnect patterns while maintaining high 3D integration density.
2Ease of manufacture
If thermal cycles are used to form SOI transistors, then transistor fabrication is achieved, but photodiode doping is degraded and well capacity is reduced
Solution Approach 1:
The patent segments the fabrication process into distinct temperature zones: photodiode formation occurs at lower temperatures to preserve doping quality, while transistor gate formation and activation occur at higher temperatures. This temporal and thermal segmentation allows each component to be processed under optimal conditions without mutual interference.
3Productivity
If fully processed pixel wafer is adhesively bonded to fully processed analog/digital companion wafer, then stacked image system is formed, but fabrication cost increases and wafer-to-wafer interconnect density decreases
Solution Approach 1:
The patent performs preliminary processing of the pixel wafer to a sufficient degree before bonding, but leaves certain high-cost steps (such as complete metal stacking and final transistor activation) to be completed after bonding. This staged approach reduces pre-bonding fabrication costs while maintaining the ability to achieve full functionality post-integration.
4Productivity
If deep through-silicon via connections are used, then wafer-to-wafer interconnect is achieved, but color-filter-array processing is affected and fabrication cost increases
Solution Approach 1:
The patent extracts the through-silicon via formation process from the conventional deep-substrate approach and repositions it to occur after bonding, using shallower via structures. This extraction eliminates the need for deep drilling through the pixel wafer that would interfere with color-filter-array processing, while still achieving the required interconnect density through the bonded interface.
Data Source
AI summary
An integrated circuit die may include bottom-gate thin-body transistors. The bottom-gate thin-body transistors may be formed in a thinned-down substrate having a thickness that is defined by shallow trench isolation structures that provide complete well isolation for the transistors. The transistors may include gate terminal contacts formed through the shallow trench isolation structures, bulk terminal contacts that are formed through the thinned substrate and that overlap with the gate contacts, and source-drain terminal contacts with in-situ salicide. Additional metallization layers may be formed over the gate/bulk/source-drain contacts after bonding.