Bottom Isolation Layout for FinFET Leakage and Capacitance Control
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, parasitic capacitance and current leakage become significant issues affecting the performance of multi-gate devices like FinFETs and GAA transistors, with existing techniques failing to adequately address these problems.
Innovation Solution
The semiconductor structure incorporates a multi-gate device with fin-like structures and bottom isolation features comprising a first and second dielectric layer, forming patterns such as a checkerboard or strip network, which mitigates parasitic capacitance and current leakage by reducing isolation feature loss during manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If existing isolation techniques are used, then manufacturing is simpler, but parasitic capacitance and current leakage increase
Solution Approach 1:
The isolation structure is segmented into multiple dielectric layers (first dielectric layer and second dielectric layer) with different materials and properties. The first dielectric layer is positioned between the gate structure and the fin base, while the second dielectric layer is positioned between source/drain regions and the fin base. This segmentation allows each layer to address specific electrical isolation needs, effectively reducing parasitic capacitance and current leakage without requiring a monolithic complex structure.
Solution Approach 2:
Different dielectric materials are selectively placed in different locations based on local electrical requirements. The first dielectric layer uses materials with specific properties to address gate-to-fin base capacitance, while the second dielectric layer uses different materials to address source/drain to fin base isolation. This local quality approach optimizes electrical performance at each critical interface without uniformly complicating the entire structure.
2Productivity
If geometry size is decreased, then production efficiency increases and costs降低, but parasitic capacitance and current leakage become more significant
Solution Approach 1:
The solution moves from a two-dimensional planar isolation approach to a three-dimensional multi-layer isolation architecture. By stacking dielectric layers vertically at the fin base region, the patent creates additional isolation dimensions that effectively reduce parasitic capacitance and current leakage without increasing the lateral footprint, thus maintaining scaling benefits while addressing electrical performance issues.
Solution Approach 2:
The multi-layer dielectric structure is formed during the fabrication process before final device operation, proactively addressing parasitic capacitance and current leakage issues that would otherwise become critical at scaled dimensions. The first and second dielectric layers are deposited and patterned in advance to establish proper electrical isolation before subsequent processing steps, preventing performance degradation from occurring during device operation.
Data Source
AI summary
A semiconductor structure includes a fin-shaped structure protruding from a substrate and including a fin base and a stack of channel layers over the fin base, an isolation feature disposed adjacent to the fin base, a first dielectric layer disposed over the isolation feature, a metal gate structure wrapping around the stack of channel layers, a gate spacer disposed over the isolation feature and along a sidewall of the metal gate structure, a second dielectric layer disposed over the fin base and adjacent to the stack of channel layers, and a source/drain feature disposed over the second dielectric layer and connected to the stack of channel layers. The metal gate structure and the gate spacer are disposed over a portion of the first dielectric layer. From a top view, the first dielectric layer and the second dielectric layer form a checkerboard pattern or a strip network pattern.