Bottom Isolation Hard Mask Layout for Backside Via Leakage Control
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Solution Overview
Problem
As semiconductor devices miniaturize, the reduced dimensions of interconnect structures lead to increased electrical resistance and potential current leakage due to the proximity of backside vias to gate electrodes, exacerbated by process variations during manufacturing.
Innovation Solution
A semiconductor structure with a modified isolation structure and a method for manufacturing it, which includes a hard mask portion with a main region and sidewall regions made of different insulating materials, effectively separating the backside via from the gate electrodes and alleviating current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the dimension of interconnect structures is reduced to achieve size miniaturization, then the integration density is improved, but the electrical resistance increases and current leakage occurs
Solution Approach 1:
The isolation structure is segmented into multiple functional regions: a first isolation region with a first dielectric material, a second isolation region with a second dielectric material having different etch selectivity, and a third isolation region. This segmentation allows different materials to be selectively removed and replaced, creating optimized isolation zones that reduce electrical resistance and prevent current leakage while maintaining miniaturization benefits
Solution Approach 2:
The patent changes the dielectric material parameters by introducing multiple dielectric layers with different etch selectivities and electrical properties. The first dielectric material is selectively removed and replaced with a low-k dielectric material, while the second dielectric material remains as an etch stop layer. This parameter change optimizes electrical performance by reducing resistance and preventing leakage in the miniaturized interconnect structures
2Reliability
If backside vias are positioned closer to gate electrodes to reduce interconnect length, then the electrical resistance is reduced, but current leakage increases due to process variations
Solution Approach 1:
The patent introduces an intermediary etch stop layer (second isolation region with second dielectric material) positioned between the low-k dielectric material and the underlying structure. This intermediary layer acts as a buffer that prevents direct interaction between the low-k material and the substrate, thereby preventing current leakage paths while allowing the low-k dielectric to reduce electrical resistance in the interconnect structures
Solution Approach 2:
The etch stop layer is placed beforehand to prevent harmful effects. By positioning this layer with different etch selectivity before the final structure is complete, it provides a protective barrier that prevents process variations from causing direct contact between conductive elements and the substrate, thereby cushioning against potential current leakage issues before they occur
3Device complexity
If a single material isolation structure is used to simplify manufacturing, then the device complexity is reduced, but the process window is limited due to lack of selective etching
Solution Approach 1:
The patent applies local quality by assigning different dielectric materials to different spatial regions of the isolation structure. The first isolation region uses a first dielectric material, the second isolation region uses a second dielectric material with different etch selectivity, and the third isolation region uses a third dielectric material. This local differentiation enables selective etching processes to access and modify specific regions without affecting others, thereby expanding the process window while maintaining manufacturing feasibility
Data Source
AI summary
A semiconductor structure includes: a first fin portion and a second fin portion; a first device and a second device which are respectively disposed on front surfaces of the first and second fin portions, each of the first and second devices including a source/drain portion; an isolation portion disposed to separate the first fin portion from the second fin portion and to separate the first device from the second device; and a hard mask portion disposed beneath a back surface of the isolation portion, and including a main region and two sidewall regions that are respectively located at two opposite sides of the main region so as to separate the main region from the first and second fin portions. The sidewall regions are made of a material different from that of the isolation portion. The main region is made of a material different from the material of the sidewall regions.