Bottom Local Interconnects for Semiconductor Wafer Wiring Density
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Solution Overview
Problem
The challenge in modern semiconductor technology is the overcrowding of wiring on semiconductor chips due to the complexity of interconnect wiring structures in ultrathin devices, particularly in CMOS scaling, where conventional embedded interconnect structures are not viable for forming interconnect wiring in thin-body silicon devices.
Innovation Solution
A semiconductor wafer with a bottom local interconnect structure is fabricated using a substrate with doped regions and a buried oxide layer, where transistors are formed with source and drain structures electrically connected through the channel layer and buried oxide layer, allowing for reduced wiring density and efficient interconnect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional embedded interconnect structures are used in thin-body silicon devices, then interconnect wiring can be formed, but wiring overcrowding occurs due to the complexity of interconnect wiring structures in ultrathin devices
Solution Approach 1:
The patent inverts the conventional interconnect approach by forming source and drain structures that extend through the channel layer to contact the substrate, rather than forming interconnect wiring on top of the device. This bottom-local interconnect structure eliminates the need for complex embedded interconnect wiring in ultrathin devices, resolving the wiring overcrowding problem while maintaining electrical connectivity.
2Adaptability or versatility
If more interconnect wiring is added to handle device complexity, then device functionality is improved, but wiring overcrowding and space constraints worsen
Solution Approach 1:
The patent moves the interconnect function from the vertical dimension (embedded wiring above the device) to the horizontal dimension (source/drain structures extending to the substrate). This dimensional shift allows complex device functionality to be achieved without increasing wiring density on the chip surface, as interconnects are formed at the bottom level rather than competing for surface area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces wiring overcrowding and enables effective interconnect formation in ultrathin devices, improving the scalability and efficiency of semiconductor chip fabrication by allowing for the integration of interconnect wiring structures at the bottom of the chip rather than on top.
Implementation Method 1
The substrate includes a first substrate region doped with a first dopant and a second substrate region doped with a second dopant
Implementation Method 2
forming a buried oxide (BOX) layer on the substrate and a channel layer formed above the BOX layer
Data Source
AI summary
A semiconductor wafer includes a substrate. The substrate includes a first substrate region doped with a first dopant and a second substrate region doped with a second dopant. The semiconductor wafer further includes a buried oxide (BOX) layer formed on the substrate and a channel layer formed above the BOX layer. A first transistor is operably disposed on the substrate in the first substrate region and a second transistor is operably disposed on the substrate in the second substrate region. First doped source and drain structures electrically connected to the substrate in the first substrate region and separated by portions of the channel layer and the BOX layer. Second doped source and drain structures electrically connected to the substrate in the second substrate region and separated by portions of the channel layer and the BOX layer.