Metal Gate Stack Structure With Bottom-Only Work-Function Metal
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Solution Overview
Problem
As transistor feature sizes decrease, the fraction of the gate stack volume occupied by the conductive metal gate electrode decreases, increasing gate resistance and reducing switching power due to the increased resistance and smaller contact area.
Innovation Solution
A method is developed to form a metal gate transistor by depositing dielectric and work-function metal layers only on the bottom wall of the gate void, eliminating the sidewall portions of these layers to increase the volume available for conductive metal gate material, which is then filled in the void, reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate stack formation is used, then the gate stack structure is formed, but the fraction of conductive metal gate electrode volume decreases as feature size decreases, increasing gate resistance
Solution Approach 1:
The patent extracts the work-function metal layer from the sidewalls of the gate stack, removing only the portions that do not contribute to electrical function. This extraction increases the relative volume of conductive metal gate electrode while maintaining the necessary work function adjustment at the semiconductor interface.
Solution Approach 2:
The patent applies local quality by maintaining work-function metal layer only where it is electrically functional (at the bottom interface with semiconductor channel) and removing it from non-functional regions (sidewalls). This localized retention optimizes the distribution of materials based on their functional requirements.
2Power
If feature size is decreased, then switching power is reduced due to shorter source-to-drain distance, but gate resistance increases due to smaller conductive metal gate volume
Solution Approach 1:
By extracting excess work-function metal from sidewalls, the patent increases the proportion of conductive metal in the gate stack, thereby maintaining lower gate resistance even as overall feature dimensions are reduced for lower switching power.
Solution Approach 2:
The patent changes the material composition parameter of the gate stack by adjusting the ratio of work-function metal to conductive metal through selective removal, optimizing electrical resistance characteristics while maintaining scaled-down dimensions for reduced power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a gate stack with a higher proportion of conductive metal gate material, reducing contact resistance and improving switching power by increasing the surface area of the conductive metal gate material.
Implementation Method 1
depositing a dielectric layer on a bottom wall and sidewalls of the gate void
Implementation Method 2
depositing a work-function metal layer on the dielectric layer on the bottom wall and the sidewalls
Data Source
AI summary
Forming a metal gate transistor includes forming a semiconductor channel in a substrate, and depositing a source electrode and a drain electrode on the semiconductor channel. The source and drain electrodes are spaced apart. Dielectric spacers are provided above the source and drain electrodes to define a gate void spanning the source and drain electrodes. A dielectric layer is deposited on a bottom wall and sidewalls of the gate void. A work-function metal layer is deposited on the dielectric layer. The work-function metal layer is etched away from the sidewalls leaving the work-function metal layer on the bottom wall to control work function between the semiconductor channel and a conductive metal gate material to be deposited. The gate void above the work-function metal layer on the bottom wall, and between the dielectric layers on the sidewalls, is filled with the conductive metal gate material.