Bottom-Pinned MRAM Composite SOT Structure for Thermal Stability
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Solution Overview
Problem
Current SOT-MRAM devices face challenges with weak magnetic stability due to top-pinned architecture, which limits their applicability, and struggle with high power consumption and slow switching speeds, especially in ultra-fast and low-power device applications.
Innovation Solution
A bottom-pinned MRAM with a composite SOT magnetic tunneling junction (CSOT-MTJ) structure, comprising a magnetic flux guiding layer, a spin Hall channel with a large positive spin Hall angle, an in-plane magnetic memory layer, a tunnel barrier layer, and a magnetic pinning stack, utilizing enhanced spin-orbit torque and Lorentz force to achieve ultra-fast writing and improved thermal stability, while eliminating the need for external magnetic fields through canted annealing or oval shaping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If top-pinned architecture is used in SOT-MRAM devices, then the device structure is simpler to manufacture, but magnetic stability becomes weak
Solution Approach 1:
The patent inverts the conventional top-pinned architecture to a bottom-pinned configuration. The magnetic pinning stack is positioned at the bottom of the MTJ structure rather than at the top, which fundamentally changes the magnetic stability characteristics while maintaining manufacturing feasibility through standard deposition processes.
Solution Approach 2:
The patent employs a composite magnetic structure with multiple layers including CoFeB, CoFe, Ru, and antiferromagnetic materials arranged in a specific stack. This composite structure enhances magnetic stability through synthetic antiparallel coupling and interfacial anisotropy while maintaining compatibility with existing manufacturing processes.
2Device complexity
If conventional SOT-MRAM writing method is used, then the device structure is simpler, but switching speed is slow and power consumption is high
Solution Approach 1:
The patent introduces a magnetic flux guiding layer with specific magnetic properties positioned locally above the spin Hall channel. This localized structure concentrates and guides magnetic flux directly to the magnetic memory layer, enhancing switching efficiency and speed without requiring changes to the overall device architecture.
Solution Approach 2:
The magnetic flux guiding layer acts as an intermediary between the spin Hall channel and the magnetic memory layer. It mediates the transfer of spin-orbit torque and guides magnetic flux, enabling faster and more efficient switching while maintaining a relatively simple device structure.
3Ease of operation
If external magnetic fields are applied for writing, then magnetic field control is achieved, but device complexity increases and power consumption increases
Solution Approach 1:
The patent enables the device to generate its own writing magnetic field through the spin Hall effect in the spin Hall channel. The in-plane current flowing through the spin Hall channel generates a perpendicular magnetic field via the spin Hall effect, eliminating the need for external magnetic field sources and reducing device complexity.
Solution Approach 2:
The patent replaces external magnetic field application (mechanical/electromagnetic system) with an in-plane current-driven spin Hall effect mechanism. This substitution eliminates the need for external magnets or coil structures, reducing device complexity while maintaining magnetic field control capability.
4Ease of manufacture
If conventional top-pinned structure is used, then manufacturing is easier, but thermal stability is insufficient for miniaturized devices
Solution Approach 1:
The patent inverts the pinning layer position to the bottom of the MTJ structure. This bottom-pinned configuration provides better thermal stability by positioning the magnetically pinned layers away from the top interface where heat and stress concentrations occur, while still using standard deposition processes for manufacturing.
Solution Approach 2:
The patent uses a composite magnetic stack with multiple materials (CoFeB, CoFe, Ru, antiferromagnetic layers) that provide enhanced thermal stability through synthetic antiparallel coupling and controlled interfacial anisotropy. This composite structure maintains manufacturing ease while significantly improving reliability for miniaturized devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables ultra-high switching speed with reduced power consumption, enhanced thermal stability, and eliminates the need for external magnetic fields, making it suitable for miniaturized devices like cache applications in CPUs, GPUs, and TPUs.
Implementation Method 1
utilizing enhanced spin-orbit torque
Implementation Method 2
magnetic flux guide in immediate proximity to a spin Hall channel
Implementation Method 3
a bottom-pinned MTJ stack
Implementation Method 4
magnetic pinning stack
Data Source
AI summary
An ultra-fast magnetic random access memory (MRAM) comprises a three terminal bottom-pinned composite SOT magnetic tunneling junction (bCSOT-MTJ) element including (counting from top to bottom) a magnetic flux guide (MFG) having a very high magnetic permeability, a spin Hall channel (SHC) having a large positive spin Hall angle, an in-plane magnetic memory (MM) layer, a tunnel barrier (TB) layer, and a magnetic pinning stack (MPS) having a synthetic antiparallel coupling pinned by an antiferromagnetic material. The magnetic writing is significantly boosted by a combined effort of enhanced spin orbit torque (SOT) and Lorentz force generated by current-flowing wire (CFW) in the SHC layer and spin transfer torque (STT) by a current flowing through the MTJ stack, and further enhanced by a magnetic close loop formed at the cross section of MFG/SHC/MM tri-layer. Such bCSOT-MTJ element will have a very fast (down to picoseconds) switching speed and consume much less power suitable level 1 or 2 cache application for SMRAM, CPU, GPU and TPU.