Bottom-Plate Sampling SAR ADC With LSB Mismatch Error Feedback
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Solution Overview
Problem
SAR ADCs face limitations in achieving high-resolution analog-to-digital conversions due to DAC element matching and comparator noise, which degrade SNDR performance, and existing solutions like oversampling and dynamic element matching are complex and costly, especially beyond 12 bits.
Innovation Solution
Implementing a bottom-plate sampling SAR ADC with a multi-bit capacitor array that includes an extra capacitor for mismatch error shaping (MES) on less significant capacitors, allowing dynamic element matching on more significant bits, and using an extra capacitor to recover lost input range and eliminate gain error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If oversampling techniques are used to improve ADC accuracy and reduce SNDR losses, then measurement precision is improved, but device complexity increases due to the need for dynamic element matching
Solution Approach 1:
The capacitor array is segmented into two distinct groups: first capacitors (C1-C4) for MSB sampling and second capacitors (C5-C8) for LSB mismatch error shaping. This segmentation allows independent optimization of each group's function, enabling MES on LSB capacitors while maintaining simple sampling on MSB capacitors, thus improving precision without proportionally increasing complexity
Solution Approach 2:
The patent implements dynamic element matching by dynamically switching the connection of LSB capacitors between different configurations during the conversion process. The LSB capacitors are dynamically reconfigured to either sample the input signal or be connected to reference voltages based on the conversion stage, enabling error shaping without requiring complex external DEM circuitry
2Measurement precision
If dynamic element matching is used to reduce SNDR losses, then measurement precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the mismatch error shaping function directly into the DAC capacitor array structure itself, rather than requiring separate external DEM circuitry. The LSB capacitors serve dual purposes: as part of the DAC structure and as the error shaping mechanism, eliminating the need for additional DEM components and reducing manufacturing cost
Solution Approach 2:
The LSB capacitors (C5-C8) are designed to perform multiple functions: they serve as part of the DAC capacitor array for normal conversion and simultaneously function as the error shaping mechanism through their dynamic reconfiguration. This multi-functionality eliminates the need for separate DEM circuitry, reducing manufacturing complexity and cost
3Measurement precision
If mismatch error shaping is implemented on less significant capacitors, then measurement precision is improved, but input range is reduced
Solution Approach 1:
The capacitor array is segmented into MSB capacitors (C1-C4) and LSB capacitors (C5-C8), with the MSB capacitors dedicated to sampling the full input range. This segmentation ensures that the input signal is sampled on capacitors that maintain the full dynamic range, while the LSB capacitors handle only the error shaping function, thus preserving input range while achieving precision improvement
Solution Approach 2:
Different parts of the capacitor array are assigned different functions with appropriate characteristics: MSB capacitors are optimized for full-range sampling, while LSB capacitors are optimized for error shaping. The MSB capacitors maintain full input range capability, while the LSB capacitors are dynamically reconfigured for error correction, achieving local optimization that preserves overall input range
Data Source
AI summary
A SAR ADC includes a DAC, a comparator and SAR circuitry, where the DAC includes MSBs encoded with first capacitors; a mismatch error shaping capacitor coupled to the MSBs; LSBs encoded with second capacitors, where a first switch set couples bottom capacitor plates of the first capacitors and the mismatch error shaping capacitor to receive an analog input voltage, a high reference voltage, or a low reference voltage in response to first DAC feedback control signals, wherein a second switch set couples bottom capacitor plates of the second capacitors to receive the high reference voltage or the low reference voltage in response to second DAC feedback control signals, and wherein the SAR circuitry is configured to feedback a mismatch error value from a previous SAR conversion cycle to the LSBs sub-DAC during a current sampling cycle.