Bottom-Plate SAR ADC With MES Capacitor Feedback for SNDR
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SAR ADC solutions face challenges in achieving high-speed analog-to-digital conversions beyond 12 bits due to limitations in DAC element matching, comparator and preamplifier noise, and reduced input range, which impair signal-to-(noise+distortion) (SNDR) performance.
Innovation Solution
A bottom-plate sampling successive approximation register (SAR) ADC with a digital-to-analog converter (DAC) component formed using a multi-bit capacitor array, where an extra capacitor is used for mismatch error shaping (MES) on the less significant capacitors, allowing dynamic element matching or calibration on the more significant bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic element matching is used to improve ADC accuracy and reduce SNDR losses, then measurement precision is improved, but device complexity increases due to logic complexity and costs
Solution Approach 1:
The capacitor array is divided into two segments: a first capacitor array for sampling the input voltage and a second capacitor array for mismatch error shaping. This segmentation allows different functions to be performed by separate capacitor groups, enabling accuracy improvement through error shaping without requiring complex dynamic element matching logic across the entire array.
Solution Approach 2:
The mismatch error shaping function is extracted from the main capacitor array and implemented using a dedicated second capacitor array. This extraction isolates the error correction mechanism from the primary sampling function, reducing the complexity burden on the main conversion path while still achieving accuracy improvements.
2Measurement precision
If more binary-weighted elements are used to achieve higher resolution, then measurement precision is improved, but device complexity increases due to more DAC elements
Solution Approach 1:
The DAC capacitor array is segmented into a first capacitor array for sampling and a second capacitor array for mismatch error shaping. This segmentation reduces the complexity burden on the main conversion path by offloading error correction to a separate, simpler structure.
Solution Approach 2:
The patent changes the functional parameters of different capacitor arrays: the first array operates in sampling mode while the second array operates in error shaping mode. This parameter differentiation allows each array to be optimized for its specific function, reducing overall complexity while maintaining high resolution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enhances SNDR performance by enabling mismatch error shaping on less significant bits, recovering lost input range, and allowing for dynamic element matching on more significant bits, thus overcoming the limitations of existing SAR ADCs.
Implementation Method 1
The DAC may be formed of an array of binary-weighted elements, such as capacitors and/or resistors
Data Source
Figure 1
Figure 2~3
Figure 4
AI summary
A SAR ADC includes a DAC, a comparator and SAR circuitry, where the DAC includes MSBs encoded with first capacitors; a mismatch error shaping capacitor coupled to the MSBs; LSBs encoded with second capacitors, where a first switch set couples bottom capacitor plates of the first capacitors and the mismatch error shaping capacitor to receive an analog input voltage, a high reference voltage, or a low reference voltage in response to first DAC feedback control signals, wherein a second switch set couples bottom capacitor plates of the second capacitors to receive the high reference voltage or the low reference voltage in response to second DAC feedback control signals, and wherein the SAR circuitry is configured to feedback a mismatch error value from a previous SAR conversion cycle to the LSBs sub-DAC during a current sampling cycle.