Bottom-Side Power Delivery Layout for Scaled MOSFET Reliability
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Solution Overview
Problem
The scaling down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electrical and reliability characteristics to maintain high-performance capabilities.
Innovation Solution
The semiconductor device incorporates a substrate with specific patterns, power lines, and penetration vias, along with a power delivery network layer, to enhance electrical connectivity and reliability, including the use of active patterns, source/drain patterns, and division structures to support efficient voltage application and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to reduce pattern size and design rule, then device integration density is improved, but operational properties deteriorate
Solution Approach 1:
The substrate is divided into multiple active regions separated by division structures (depression regions or insulation films). This segmentation allows each active region to be independently optimized and maintained at appropriate dimensions, preventing the operational property deterioration that would result from uniform scaling down of all structures. The division structures create isolated zones where transistors can operate reliably without being constrained by overall device size reduction.
Solution Approach 2:
Different regions of the substrate are given different properties through the division structures. Active regions contain transistor structures while division structures provide isolation. This local differentiation allows specific areas to be optimized for high-density integration while other areas maintain structural integrity and operational reliability, resolving the contradiction between small pattern size and good operational properties.
2Productivity
If MOS-FETs are scaled down, then integration density is improved, but electrical characteristics deteriorate
Solution Approach 1:
The division structures extend in the vertical dimension (depth into the substrate) as well as horizontal dimensions. Depression regions penetrate into the substrate and insulation films have substantial thickness, creating three-dimensional isolation barriers. This vertical dimension provides additional electrical isolation without consuming horizontal space that would be needed for transistor integration, allowing high integration density while maintaining electrical characteristics.
Solution Approach 2:
The substrate is segmented into electrically isolated active regions by division structures. This segmentation prevents electrical interference between adjacent transistor structures, maintaining reliable electrical characteristics even when transistors are densely packed. Each active region can be independently optimized for electrical performance while contributing to overall high integration density.
3Reliability
If more power lines and penetration vias are added to improve electrical connectivity, then device complexity increases
Solution Approach 1:
The division structures serve multiple functions simultaneously: they provide electrical isolation between active regions, serve as substrates for power lines, and act as pathways for penetration vias. By making the division structures multi-functional, the patent reduces overall device complexity because a single structural element performs multiple roles that would otherwise require separate components.
Solution Approach 2:
Power lines are merged with division structures, with power lines formed on top of or within division structures. Penetration vias are merged with division structures, using the same vertical pathways. This merging reduces the total number of discrete structures needed, simplifying the overall device architecture while improving electrical connectivity through the power delivery network.
Data Source
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AI summary
A semiconductor device may include first active patterns adjacent to each other on a substrate, first source/drain patterns respectively on the first active patterns and adjacent to each other, a first division structure and a second division structure crossing the first active patterns and arranged on the substrate such that adjacent ones of the first source/drain patterns are interposed between the first division structure and the second division structure, a first penetration via between adjacent ones of the first source/drain patterns, a first power line on the first penetration via and electrically connected to the first penetration via, a power delivery network layer on a bottom surface of the substrate, and a first lower penetration via between the power delivery network layer and the first penetration via.