Bottom-Seeded Dummy Gate Deposition for Voidless FinFET Trenches
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in the manufacturing of FinFETs due to issues such as the formation of seams and voids during the gap-filling process in high aspect ratio trenches, which affect the integration density and performance of electronic components.
Innovation Solution
A method involving the formation of a bottom seed structure using a higher order silane precursor, followed by a bottom-up deposition process with a chlorine-containing silicon precursor, which allows for seamless and voidless filling of trenches without growing the dummy gate material from the dielectric layer, thereby addressing the issues of seams and voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional gap-filling processes are used in high aspect ratio trenches, then manufacturing process simplicity is maintained, but seams and voids form during filling, reducing manufacturing precision and device reliability
Solution Approach 1:
The gap-filling process is divided into multiple sequential steps: first forming a bottom seed structure, then performing bottom-up deposition to fill the trench. This segmentation allows each step to be optimized independently, ensuring complete filling without seams or voids while maintaining process control
Solution Approach 2:
A bottom seed structure is formed in advance within the trench before the main gap-filling deposition. This preliminary action provides a foundation that enables subsequent material to deposit uniformly and completely fill the high aspect ratio trench, preventing void formation
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated, but seam and void formation during gap-filling becomes more problematic, affecting device reliability
Solution Approach 1:
The bottom seed structure is formed beforehand in the trench, providing a reliable foundation that ensures complete and uniform filling even as trench dimensions shrink. This preliminary preparation prevents void formation that would compromise device reliability at smaller feature sizes
Solution Approach 2:
The patent employs bottom-up deposition methodology that replaces conventional filling approaches. This substitution enables atomic-layer precise material deposition that eliminates seam formation, ensuring reliability as features scale down
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density and performance of FinFETs by reducing the formation of seams and voids, leading to improved manufacturing efficiency and device reliability.
Implementation Method 1
condensing the higher order silane into a flowable silicon film
Implementation Method 2
depositing the flowable silicon film in the recess
Implementation Method 3
performing a bottom-up deposition using a second flowable silicon material in the recess and over the bottom structure
Data Source
AI summary
A system and methods of manufacturing semiconductor devices is described herein. The method includes forming a recess between fins in a substrate and forming a dielectric layer over the fins and in the recess. Once the dielectric layer has been formed, a bottom seed structure is formed over the dielectric layer within the recess and the dielectric layer is exposed along sidewalls of the recess. A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process without growing the dummy gate material from the dielectric layer exposed along sidewalls of the recess.