Bottom-Select-Gate Memory Layout for 3D Cell String Connectivity

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Solution Overview

Problem

Current 3D memory devices face challenges in efficiently forming staircase structures with vertically oriented electrodes and select gates, which affect the electrical connectivity and separation of memory cells, leading to limitations in storage density and performance.

Innovation Solution

The proposed solution involves forming a bottom-select-gate (BSG) structure with cut slits and gate-line slits on a substrate, creating finger regions with alternating electrode/insulating layer pairs, and connecting these regions through gate-line sub-slits to establish electrical connections between cell strings, while maintaining separate select gates of varying heights.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vertically oriented electrodes and select gates are formed in staircase structures, then electrical connectivity between memory cells is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidstaircase structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the continuous BSG structure into multiple segments by forming cut slits that extend through the BSG thickness. This segmentation allows independent control of different BSG portions and simplifies the formation of vertically oriented electrodes and select gates in staircase structures, reducing manufacturing complexity while maintaining electrical connectivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different structural configurations to different regions of the memory device. Specifically, cut slits are formed in certain portions of the BSG structure to create localized segments, while other regions maintain continuous BSG structures. This local differentiation optimizes electrical connectivity in critical areas while reducing overall device complexity.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If cut slits are formed through the BSG structure to segment it, then manufacturing ease and electrical control are improved, but electrical connectivity between segmented regions may be compromised

Engineering Contradiction:
ImproveBSG structure formationVSAvoidelectrical connectivity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent uses gate-line slits as intermediary structures that extend through both the BSG structure and cell-layer structure into the substrate. These gate-line slits serve as conductive pathways that bridge the gaps created by cut slits, maintaining electrical connectivity between segmented BSG regions while allowing independent control of each segment.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a nested structure where gate-line slits are formed within and through the BSG structure segments. The gate-line slits are positioned to extend through the cut slit regions, creating a nested configuration that maintains electrical pathways while preserving the segmented architecture for independent control.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Adaptability or versatility

If gate-line slits with sub-slits are formed to distinguish finger regions, then cell separation and selective control are improved, but device complexity increases

Engineering Contradiction:
Improveselective control of memory cellsVSAvoidgate-line slit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides gate-line slits into multiple sub-slits that are arranged to distinguish and separate different finger regions. Each sub-slit corresponds to a specific finger region, enabling selective control of memory cells in different regions. This segmentation provides adaptability for independent region control while using a systematic pattern that manages device complexity.

Inventive Principle:
Principle #1Segmentation

4Quantity of substance

If BSG segments of varying heights are formed, then storage density is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvestorage densityVSAvoidBSG segment height control
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent forms BSG segments of varying heights by performing preliminary etching and deposition steps that establish different height levels before final device assembly. Cut slits are formed to defined depths, and subsequent material deposition creates BSG portions at different heights, enabling increased storage density while managing manufacturing precision through staged processing.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11749737B2Memory device with bottom-select-gate structure and method for forming the same
Publication Date: 2023.09.05 YANGTZE MEMORY TECH CO LTD
  • US11749737B2 patent drawing
  • US11749737B2 patent drawing
  • US11749737B2 patent drawing

AI summary

Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.