Bottom Side Interposer for Structurally Balanced IC Package
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Solution Overview
Problem
Large scale 2.5D & 3D high performance packaging solutions for semiconductor circuits face substantial thermal warp issues due to coefficient of thermal expansion (CTE) mismatches between materials, leading to solder yield reduction, delamination, and other detrimental chip/package interactions, despite the use of stiffeners and intermediate CTE organic chip carriers.
Innovation Solution
A bottom side interposer with a CTE similar to or intermediate between the semiconductor chips and the chip carrier is attached to the chip carrier using a lamination adhesive sheet and transient liquid metal paste deposits, creating a structurally balanced package that reduces thermal warp and increases robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If large perimeter stiffeners are applied to mitigate CTE mismatch induced warp, then package structural strength is improved, but substantial warp may still remain and device complexity increases
Solution Approach 1:
A bottom side interposer is introduced as an intermediary component between the chip carrier and the PCB. This interposer has a CTE specifically selected to be intermediate between the chip carrier CTE and the PCB CTE, creating a gradual CTE transition that reduces thermal warp without requiring complex stiffening structures
Solution Approach 2:
The CTE of the bottom side interposer is specifically engineered to fall between the CTE values of the chip carrier and the PCB. By changing the material parameter (CTE) of the interposer, the system achieves a balanced thermal expansion profile that minimizes warp during reflow and thermal cycling
2Stability of the object's composition
If intermediate CTE organic chip carriers are used to minimize CTE mismatch induced warp, then thermal warp is reduced, but substantial warp may still exist after reflow assembly due to general imbalance of CTE attributes
Solution Approach 1:
The bottom side interposer serves as a mediator that balances the CTE attributes of the entire package assembly. By positioning this interposer at the bottom side and selecting its CTE to be intermediate between the chip carrier and PCB, the system achieves structural balance that prevents warp during reflow assembly and thermal cycling
Solution Approach 2:
Rather than relying solely on symmetric intermediate CTE laminates on both sides, the invention introduces an asymmetric solution by placing a bottom side interposer specifically configured with an intermediate CTE. This asymmetric approach creates structural balance by compensating for the CTE mismatch at the critical bottom interface
3Adaptability or versatility
If large scale 2.5D & 3D high performance packaging solutions are implemented, then wiring redistribution function is improved, but substantial warp occurs due to CTE difference between materials
Solution Approach 1:
The bottom side interposer acts as a mediator that enables large scale 2.5D and 3D packaging solutions by providing a structurally balanced interface. Its intermediate CTE allows the package to accommodate large interposers and multiple chip layers while maintaining thermal stability and preventing warp
Solution Approach 2:
The package assembly becomes a composite structure comprising the chip carrier, bottom side interposer with intermediate CTE, and PCB. This composite material approach allows the system to leverage the advantages of different materials (wiring redistribution capability of interposers, structural support of chip carrier, connectivity of PCB) while the intermediate CTE interposer ensures thermal compatibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The balanced CTE structure minimizes thermal warp, enhances package robustness, and reduces the need for costly warp control methods, thereby improving solder yield and preventing chip/package interactions such as cracking and delamination.
Implementation Method 1
The bottom side interposer has a coefficient of thermal expansion (CTE) that is similar to the chips and top side interposer, or tailored to have a CTE intermediate to the chips and the chip carrier
Implementation Method 2
The bottom side interposer is attached to the chip carrier with a lamination adhesive sheet and transient liquid metal paste deposits
Data Source
AI summary
A bottom side interposer provides a structurally balanced chip carrier module to reduce thermal warp and increase package robustness. The bottom side interposer is attached to the bottom of a chip carrier which carries semiconductor chips on the top side of the chip carrier. The top side of the chip carrier typically includes a top side interposer between the semiconductor chips and the chip carrier. The bottom side interposer has a coefficient of thermal expansion (CTE) that is similar to the chips and top side interposer, or tailored to have a CTE intermediate to the chips and the chip carrier. Pads on the bottom side interposer may be plated or fitted with solder balls to complete the module so the module can be connected to a printed circuit board.