Bottom Source Power MOSFET Substrateless Manufacturing
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Solution Overview
Problem
Existing semiconductor device manufacturing methods for bottom source power MOSFETs require complex masking processes and cannot efficiently achieve a substrateless configuration with the source electrode exposed at the bottom and the drain and gate electrodes exposed at the top, while preventing short circuits between them.
Innovation Solution
A manufacturing method where the semiconductor chip is flipped with the source electrode formed at the bottom and the drain and gate electrodes at the top, using a through via to expose the gate electrode partially and ensuring electrical insulation between them, reducing the number of masks needed and preventing short circuits by using insulation layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional bottom source power MOSFET manufacturing method is used, then the source electrode can be exposed at the bottom, but the manufacturing process becomes complex with multiple masking steps required
Solution Approach 1:
The patent inverts the conventional manufacturing sequence by first forming the gate electrode and then creating the through-via to expose it, rather than forming the source electrode first and subsequently exposing the gate. This inversion of the fabrication sequence eliminates the need for complex masking steps while achieving the same bottom-source configuration.
Solution Approach 2:
The patent segments the gate electrode formation into two distinct parts: the main gate electrode body formed on the first surface, and the exposed portion formed through the through-via on the second surface. This segmentation allows independent formation of each part without requiring complex masking to define their relative positions.
2Productivity
If the chip is thinned to substrateless level, then the device achieves a compact configuration, but the risk of short circuits between electrodes increases
Solution Approach 1:
The patent introduces an insulation layer as an intermediary substance filling the through-via and surrounding the exposed gate electrode portion. This insulation layer acts as a mediator that electrically isolates the gate electrode from the source and drain electrodes, preventing short circuits while enabling the compact substrateless configuration.
Solution Approach 2:
The patent applies preliminary protective action by forming the insulation layer around the gate electrode before final electrode connections are made. This preliminary insulation prevents potential short circuits between the gate and other electrodes, addressing the reliability concern before the device is fully assembled.
3Ease of operation
If the gate electrode is exposed through a through via, then access to the gate is provided from the top, but the manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary action by forming the through-via opening and the insulation layer structure before forming the exposed gate electrode portion. This preliminary preparation establishes precise geometric constraints that guide the subsequent gate metal deposition, ensuring accurate alignment without requiring high-precision masking steps.
Solution Approach 2:
The insulation layer structure serves as a self-aligning template that automatically defines the position and shape of the exposed gate electrode portion. The gate metal naturally conforms to this pre-formed insulation structure, eliminating the need for external masking to control alignment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, reduces the risk of short circuits, and allows for a substrateless chip configuration, enabling effective electrical connectivity and efficient production of bottom source power MOSFET devices.
Implementation Method 1
The source electrode bump is made of a metal on the exposed portion of source metal by electroplating.
Data Source
AI summary
A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.