Bottom Spacer Formation for Vertical Transistors
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Solution Overview
Problem
Conventional vertical transistors face challenges in minimizing step coverage of bottom spacer material, leading to variations in channel length and junction location, which affects the precision of semiconductor structures.
Innovation Solution
A bilayer of silicon dioxide and silicon nitride is formed on semiconductor fins, with the silicon nitride layer being carbonized and then selectively removed to create a spacer structure that minimizes step coverage, using the remaining silicon dioxide and nitride layers as etch masks to define the bottom spacer, thereby reducing variations in channel length and junction location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional vertical transistors use bottom spacer material on sidewalls of the vertical semiconductor pillar, then the spacer provides structural support and defines the channel region, but step coverage of the bottom spacer material causes variation in channel length and junction location
Solution Approach 1:
The bottom spacer structure is segmented into multiple distinct layers: a first bottom spacer layer (silicon nitride) and a second bottom spacer layer (silicon dioxide). This segmentation allows each layer to be selectively removed or retained based on its specific function, enabling precise control over the final spacer configuration and minimizing step coverage variations.
Solution Approach 2:
Different materials are used at different locations of the bottom spacer structure to achieve local optimization. The silicon nitride layer provides robust sidewall coverage, while the silicon dioxide layer provides planar coverage on top of the source/drain regions. This local quality differentiation allows selective removal of vertical portions while maintaining horizontal portions, precisely controlling the final spacer geometry.
2Manufacturing precision
If the bottom spacer material is removed from the sidewalls of the vertical semiconductor pillar, then step coverage is reduced, but portions of the bottom spacer material above the bottom source/drain region are also removed
Solution Approach 1:
The etch selectivity parameter is changed by introducing a second bottom spacer layer with different etch resistance properties. The silicon dioxide layer has different etch selectivity compared to silicon nitride, allowing selective removal of vertical portions of one material while preserving the other. This parameter change enables precise control over which portions of the spacer structure are removed.
Solution Approach 2:
The bottom spacer structure uses a composite of two different materials (silicon nitride and silicon dioxide) with complementary properties. Silicon nitride provides excellent sidewall adhesion and etch resistance, while silicon dioxide provides good planar coverage and different etch selectivity. The composite structure allows selective removal of vertical portions while maintaining the integrity of the remaining spacer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes step coverage and reduces variations in channel length and junction location, enhancing the precision and reliability of vertical transistors.
Implementation Method 1
An upper surface of each horizontal portion of the silicon nitride layer is then carbonized
Implementation Method 2
thereafter the vertical portions of the silicon dioxide layer are removed from sidewalls of the at least one semiconductor fin utilizing each remaining portion of the silicon nitride layer as an etch mask
Data Source
AI summary
A bilayer of silicon dioxide and silicon nitride is formed on exposed surfaces of at least one semiconductor fin having a bottom source/drain region located at the footprint, and on each side, of the at least one semiconductor fin. An upper surface of each horizontal portion of the silicon nitride layer is then carbonized, and thereafter non-carbonized vertical portions of the silicon nitride layer are removed. Next, the carbonized portions of the silicon nitride layer are removed, and thereafter the vertical portions of the silicon dioxide layer are removed from sidewalls of the at least one semiconductor fin utilizing each remaining portion of the silicon nitride layer as an etch mask A bottom spacer structure is provided on each bottom source/drain region in which each bottom spacer structure includes a remaining portion of the silicon dioxide layer and the remaining portion of the silicon nitride layer.