Bottom-Up Contact Plug Filling for Void-Free Semiconductor Contacts
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced feature sizes, challenges arise in forming low-resistance contact plugs that withstand chemical mechanical polishing (CMP) processes without peeling or corrosion, while also enhancing gapfill capability and reducing contact plug resistance.
Innovation Solution
The formation of low-resistance contact plugs is achieved through non-conformal and selective deposition of barrier layers, eliminating barrier layers, and using bottom-up deposition processes, along with forming alloy or non-alloy interfaces between conductive plugs and vias, which includes the use of materials like Ru, Ir, Ni, Os, Rh, Al, Mo, W, Co, and their combinations, deposited in a controlled manner to minimize void formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional barrier layers are deposited conformally in contact plugs, then adhesion and protection are improved, but void formation increases and gapfill capability deteriorates
Solution Approach 1:
The patent inverts the conventional conformal deposition approach by using non-conformal, bottom-up deposition. Instead of depositing uniformly from all surfaces, the conductive material is deposited selectively from the bottom of the contact plug opening upward, which eliminates void formation while maintaining adhesion at the critical interface between the contact plug and the underlying structure.
Solution Approach 2:
The patent applies different deposition qualities to different regions of the contact plug. The bottom-up deposition ensures high-quality material accumulation at the bottom interface where adhesion is critical, while avoiding excessive material buildup on sidewalls that would cause voids. This localized control of material deposition resolves the contradiction between adhesion and gapfill capability.
2Manufacturing precision
If barrier layers are eliminated to improve gapfill capability, then void formation is reduced, but adhesion and protection during CMP deteriorate
Solution Approach 1:
The patent introduces a specially engineered conductive material layer that serves as both the fill material and the adhesion/promotion layer. This intermediary layer performs the dual function of providing mechanical adhesion during CMP processing while enabling void-free gapfill through its controlled deposition characteristics, replacing the need for separate barrier layers.
Solution Approach 2:
The conductive material layer is designed to perform multiple functions simultaneously: it acts as the electrical conductor, the adhesion promoter during CMP, and the structural fill material. This multi-functionality eliminates the need for separate barrier layers while maintaining both gapfill capability and CMP process resistance.
3Reliability
If contact plug resistance is reduced by increasing conductive material, then electrical performance improves, but peeling and corrosion during CMP increase
Solution Approach 1:
The patent performs preliminary surface treatment and controlled deposition to create an optimized interface structure before the CMP process. The bottom-up deposition ensures proper material orientation and density at the interface, and the controlled thickness and composition of the conductive material layer are established in advance to provide both low resistance and CMP process stability, preventing peeling and corrosion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact plug resistance and prevents peeling or damage during CMP, while improving gapfill capability, resulting in reliable electrical connections.
Implementation Method 1
non-conformal and selective deposition of barrier layers, eliminating barrier layers, and using bottom-up deposition processes
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.