Deep Trench Polysilicon Isolation With Void-Free Bottom-Up Growth
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Solution Overview
Problem
Current deep trench isolation (DTI) structures in integrated chips face issues with void formation during polysilicon growth, leading to compromised mechanical and electrical properties, and require costly and damaging chemical mechanical planarization (CMP) processes to achieve a flat surface.
Innovation Solution
A selective polysilicon growth process is employed that grows polysilicon in a bottom-up direction within the DTI structure, eliminating voids and eliminating the need for CMP by ensuring a flat top surface, thereby enhancing the reliability and efficiency of DTI structures for electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional polysilicon growth is used to fill deep trenches, then the trench can be filled with polysilicon material, but voids form during the growth process compromising mechanical and electrical properties
Solution Approach 1:
The patent applies bottom-up growth instead of conventional top-down polysilicon filling. By growing polysilicon from the trench bottom upward along the sidewalls, the method eliminates void formation that occurs with conventional approaches, ensuring complete filling and improved reliability of the isolation structure
Solution Approach 2:
The patent changes the growth direction parameter from top-down to bottom-up, and controls growth rate parameters to ensure polysilicon grows uniformly along the trench sidewalls without forming voids, thereby improving both filling quality and structural reliability
2Manufacturing precision
If chemical mechanical planarization is applied to achieve a flat surface, then surface flatness is improved, but the process is costly and damages the underlying structure
Solution Approach 1:
The patent performs preliminary action by controlling the polysilicon growth process to inherently form a flat top surface from the beginning. The bottom-up growth method ensures the surface self-planarizes during growth, eliminating the need for subsequent CMP processing and avoiding associated costs and damage
Solution Approach 2:
The patent replaces the mechanical CMP process with a controlled chemical growth process. Instead of using mechanical abrasion to achieve flatness, the polysilicon growth conditions are optimized to naturally produce a flat surface, substituting mechanical processing with a controlled deposition process
3Reliability
If deep trench isolation structures are implemented for electrical isolation, then device performance is improved, but void formation compromises the isolation effectiveness
Solution Approach 1:
The patent inverts the conventional filling approach by growing polysilicon from bottom-up instead of top-down. This ensures complete trench filling without voids, achieving the required isolation effectiveness and structural quality simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in DTI structures that provide effective electrical isolation between semiconductor devices without voids, improving mechanical and electrical properties and reducing manufacturing time and costs by eliminating the need for CMP.
Implementation Method 1
growing polysilicon in the trench and between the insulator liners, such that the polysilicon grows from the horizontally extending surface of the base layer towards a top surface of the active layer
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.


