Bottom-Up Source/Drain Contacts for Low-Resistance FinFET Filling

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Solution Overview

Problem

The semiconductor industry faces challenges in forming source/drain contacts for FinFETs, particularly in achieving low contact resistance and high device performance due to the complex three-dimensional design and the need for precise alignment of contact plugs with the source/drain regions.

Innovation Solution

The method involves forming source/drain epitaxial layers on fin structures and then depositing metal contact plugs using a capillary condensation CVD process, which allows for bottom-up deposition and filling of narrow gaps between alloy layers on neighboring semiconductor fins, thereby reducing contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional deposition methods are used to form contact plugs, then the manufacturing process is simpler, but the contact resistance is higher and the filling of narrow gaps is insufficient

Engineering Contradiction:
Improvecontact resistanceVSAvoiddeposition process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent changes the deposition parameters by using chemical vapor deposition (CVD) at controlled temperatures and pressures to achieve bottom-up filling behavior. The process parameters are optimized to enable selective deposition in narrow gaps while maintaining manufacturability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent utilizes phase transitions of deposition materials from vapor phase to solid phase during CVD processing. This phase transition enables the material to condense and fill narrow gaps effectively, achieving low contact resistance through controlled condensation in the gap regions

Inventive Principle:
Principle #36Phase transitions

2Productivity

If top-down deposition is used, then the deposition process is faster, but seam volume is larger and contact resistance is higher

Engineering Contradiction:
Improvedeposition speedVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent inverts the conventional top-down deposition approach by implementing bottom-up deposition. Instead of filling gaps from the top surface downward, the deposition starts from the bottom of the narrow gaps and grows upward, ensuring complete gap filling and reducing seam volume for lower contact resistance

Inventive Principle:
Principle #13The other way round (Inversion)

3Reliability

If narrow gaps between alloy layers are not properly filled, then the manufacturing process is simpler, but the contact resistance increases and device performance decreases

Engineering Contradiction:
Improvedevice performanceVSAvoidgap filling precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces an intermediary deposition process using CVD that acts as a mediator between the alloy layers. This intermediary material fills the narrow gaps and creates a conductive pathway, improving contact resistance without requiring direct contact between the alloy layers themselves

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in reduced source/drain contact resistance, improved device performance, and enhanced bottom-up deposition with reduced seam volume, contributing to more efficient semiconductor device manufacturing.

Implementation Method 1

depositing metal contact plugs using a capillary condensation CVD process, which allows for bottom-up deposition and filling of narrow gaps between alloy layers

Methodology Applied
Scientific EffectCapillary condensation: Capillary Condensation

Implementation Method 2

depositing metal contact plugs using a capillary condensation CVD process

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS20250203976A1Semiconductor device with source/drain contact formed using bottom-up deposition
Publication Date: 2025.06.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250203976A1 patent drawing
  • US20250203976A1 patent drawing
  • US20250203976A1 patent drawing

AI summary

A device includes a channel region, a gate structure over the channel region, a source/drain feature adjacent the channel region, an interlayer dielectric (ILD) layer disposed over the source/drain feature, and a source/drain contact extending through the ILD layer to electrically couple to the source/drain feature. The source/drain contact is spaced apart from the ILD layer by a metal-containing layer having a composition different from a composition of the source/drain contact. The device further includes a metal silicide layer disposed between the source/drain contact and the source/drain feature, and a nitridated metal silicide layer disposed between the metal silicide layer and the source/drain contact.