Boundary Dielectric Bodies for CMP Planarization Support
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Solution Overview
Problem
Current semiconductor manufacturing processes for integrated circuits (ICs) result in non-uniform conductive layers and surface damage at boundary regions due to chemical-mechanical polishing (CMP), leading to residue contamination and potential device failure.
Innovation Solution
Incorporating a plurality of dielectric bodies within the semiconductor substrate at the boundary region, which are co-planar with the substrate surface, providing sufficient support during planarization and preventing substrate damage, while also forming recess rings to improve saturation current performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If chemical-mechanical polishing (CMP) is used to planarize the conductive layer, then a planar surface is achieved, but substrate damage and non-uniform conductive layers occur at boundary regions
Solution Approach 1:
Dielectric bodies are formed at boundary regions before the CMP process to provide preliminary support and prevent substrate damage during planarization. This preliminary structural preparation ensures that the polishing process can proceed without causing oxide damage or non-uniform conductive layer formation at vulnerable boundary areas.
Solution Approach 2:
Dielectric bodies act as intermediary support structures between the polishing pad and the substrate at boundary regions. These intermediaries distribute the mechanical stress during CMP, preventing direct contact damage to the substrate while still allowing the polishing process to achieve planarization of the conductive layer.
2Shape
If CMP is performed on boundary regions, then planarization is achieved, but residue contamination and shorting issues occur
Solution Approach 1:
Masking layers are applied to boundary regions before CMP to preliminarily protect these areas from polishing. This prevents residue contamination and shorting issues by excluding the polishing process from boundary regions where such problems are most likely to occur, while still allowing planarization of the main conductive layer area.
Solution Approach 2:
The boundary regions are extracted from the polishing process by applying masking layers. This separation allows the CMP process to focus on the main conductive layer area where uniformity is critical, while boundary regions are protected from generating residue contamination and shorting issues.
3Productivity
If device size is scaled down to increase integration, then more components are integrated, but boundary region damage becomes more severe
Solution Approach 1:
Different structural qualities are applied to different regions: dielectric bodies are specifically placed at boundary regions to provide localized support, while the main device areas maintain their standard structure. This local quality enhancement protects vulnerable boundary regions from damage during scaling and CMP processes, enabling higher integration density without proportionally increasing boundary damage risk.
Solution Approach 2:
Dielectric bodies are formed in advance at boundary regions before device fabrication and CMP processes. This preliminary structural reinforcement allows subsequent scaling and processing to proceed without causing severe boundary region damage, thereby enabling higher integration density while maintaining reliability.
Data Source
AI summary
The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region.