Bit Block Stream Error Detection With Boundary Markers and Parity Checks

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Solution Overview

Problem

Current bit error detection methods in M/N bit block switching scenarios face challenges of high implementation difficulty and low bearer efficiency, particularly in accurately measuring bit error rates and tolerating bit block insertions or deletions during synchronization, which affects user service and bandwidth efficiency.

Innovation Solution

A bit block stream bit error detection method that involves sending boundary bit blocks with parity check results, allowing for dynamic configuration of detection periods and precision, and using algorithms like xBIP-y or flexBIP-z to ensure error detection with minimal impact on user service and maximum bearer efficiency, even in non-end-to-end paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If packet-based CRC detection is used, then error detection capability is improved, but bearer efficiency deteriorates due to fixed frame overhead

Engineering Contradiction:
Improveerror detection capabilityVSAvoidbearer efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the bit block stream into fixed-size N-bit blocks and performs error detection on each block independently using boundary markers. This allows error detection at the block level rather than requiring complete Ethernet packets, enabling continuous monitoring without waiting for packet boundaries and improving bearer efficiency while maintaining error detection capability.

Inventive Principle:
Principle #1Segmentation

2Reliability

If BIP check overhead is added to each frame, then bit error detection is improved, but bearer efficiency deteriorates due to rigid overhead occupation

Engineering Contradiction:
Improvebit error detectionVSAvoidbearer efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent uses dynamic configuration of detection parameters including variable block size N, variable monitoring section sizes (m and n bits), and configurable boundary marker positions. This dynamic approach allows the system to adapt to different service requirements and optimize the balance between error detection capability and bearer efficiency, unlike rigid BIP overhead schemes.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If continuous packet monitoring is performed to measure BER, then measurement precision is improved, but detection time deteriorates when user service bandwidth is low

Engineering Contradiction:
Improvebit error rate measurement accuracyVSAvoiddetection time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent enables continuous error detection by monitoring every N-bit block in the bit block stream without requiring complete Ethernet packets or long accumulation periods. By using boundary markers to delimit blocks and performing detection on each block as it passes, the system achieves continuous measurement that is independent of user service packet arrival rates, eliminating the detection time problem at low bandwidths.

Inventive Principle:
Principle #20Continuity of useful action

4Reliability

If block-by-block processing is used for error detection, then error detection capability is improved, but device complexity increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes boundary markers from the bit block stream before error detection processing. This extraction simplifies the processing by eliminating the need to interpret and handle boundary marker bits during the parity check calculations, reducing processing complexity while maintaining the ability to detect errors in the data blocks between markers.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11463104B2Bit block stream bit error detection method and device
Publication Date: 2022.10.04 HUAWEI TECH CO LTD
  • US11463104B2 patent drawing
  • US11463104B2 patent drawing
  • US11463104B2 patent drawing

AI summary

A method includes: sending a first boundary bit block; sequentially sending an Ith bit block; determining a first parity check result and a second parity check result, where a check object of the first parity check result includes m consecutive bits of each bit block in the N bit blocks, a check object of the second parity check result includes n consecutive bits of each bit block in the N bit blocks, and at least one of m and n is greater than or equal to 2; and sending a second boundary bit block, the first parity check result, and the second parity check result.