Boundary Scan Cascaded Firmware Loading via Controllable Physical Connections
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Solution Overview
Problem
Current methods for online firmware loading on printed circuit board assembly (PCBA) production lines, such as JTAG and IAP modes, face limitations due to hardware interface compatibility and complexity, leading to inefficient firmware updates and increased development costs.
Innovation Solution
A system and method for online cascaded firmware loading based on boundary scan, utilizing a host computer, TAP controller, and printed circuit boards with master controller chips and chips to be loaded, where controllable physical connections are redefined as loading buses to facilitate efficient firmware updates across multiple boards without requiring additional hardware or complex software development.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the JTAG mode is used to load firmware, then the standard JTAG interface with four physical lines can be used, but chips with SWD standard interface (only two physical lines) cannot be directly interfaced or cascaded for online loading
Solution Approach 1:
The patent makes the SWD interface multi-functional by enabling it to perform both its original debug function and firmware loading function. The boundary scan chain, originally designed for testing, is repurposed to carry firmware data during loading operations, allowing the same physical interface to serve multiple purposes without requiring additional dedicated loading pins.
Solution Approach 2:
The boundary scan chain acts as an intermediary mechanism between the SWD interface and the firmware loading process. By inserting boundary scan cells into the data path, the patent creates a mediation layer that enables firmware transmission through the limited SWD interface, effectively bridging the gap between the two-line SWD standard and the requirements for firmware loading.
2Adaptability or versatility
If the IAP mode is used to load firmware, then the loading interface can be customized, but additional master controller chip is required and development cost increases
Solution Approach 1:
The patent enables the target chip to perform firmware loading autonomously through its existing boundary scan infrastructure, without requiring an external master controller chip. The boundary scan chain itself provides the control and data transmission capabilities needed for loading, making the system self-sufficient and eliminating the need for additional controller hardware and associated software development.
Solution Approach 2:
The patent recovers and repurposes the boundary scan infrastructure, which was originally designed for testing purposes, to perform firmware loading functions. By discarding the conventional approach of requiring separate loading hardware and instead recovering the utility of the existing boundary scan cells, the patent eliminates additional development costs while maintaining loading functionality.
3Productivity
If multiple chips are cascaded for online loading, then parallel loading can be achieved, but the communication process becomes more complicated and partial loading rate is sacrificed
Solution Approach 1:
The patent merges the boundary scan chain functionality with the firmware loading process, combining testing infrastructure with data loading operations. By merging these functions into a single unified process that operates through the existing boundary scan protocol, the patent simplifies the communication process while maintaining the ability to load multiple chips in parallel through the cascaded configuration.
Data Source
AI summary
When a host computer determines that a firmware version to be loaded is higher than a firmware version of each chip to be loaded, the host computer sends a loading flag to the chips to be loaded to enable the chips to be loaded enters a loading mode. The host computer redefines multiple controllable physical connections between each chip to be loaded entering the loading mode and a master controller chip connected thereto so that they act as loading buses. Each chip to be loaded executes a loading process according to a frame period and a frame count to receive the load file completely and then executes the IAP command to program its ROM. When each chip to be loaded finishes the loading process, each chip to be loaded jumps out of the load mode, and the host computer restores the definitions of the plurality of controllable physical connections.