Boundary Scan Cell Initialization Logic for I/O Characterization
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Solution Overview
Problem
Current methods for testing integrated circuits (ICs) are limited in their ability to efficiently characterize input/output (I/O) signals and propagation times, particularly in JTAG-compliant ICs, which require more advanced techniques to perform speed testing and I/O characterization without significant modifications to existing architectures.
Innovation Solution
A test system and method utilizing boundary scan cells with initialization logic, bi-directional elements, and clock shaping systems to capture state changes within a single clock cycle, enabling efficient I/O characterization and speed testing by adjusting the test clock signal's rising edge during a predefined test mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional boundary scan cells are used for testing, then the IC can be tested for functionality, but the ability to accurately measure I/O signal propagation times and characterize signals at high speeds is limited
Solution Approach 1:
The boundary scan cell is divided into multiple storage elements (first storage element and second storage element) connected in series, with each element serving a specific function in the measurement process. This segmentation allows for more precise timing measurement while maintaining manageable complexity through modular design.
Solution Approach 2:
Initialization logic is introduced as an intermediary component between the storage elements to control the measurement process. This intermediary enables the system to transition between different operating states (first operating state for normal operation, second operating state for measurement), facilitating accurate propagation time measurement without requiring fundamental changes to the overall cell structure.
2Measurement precision
If the test clock signal has a fixed duty cycle, then the normal operation is maintained, but the ability to capture state changes within a single clock cycle for high-resolution timing measurement is limited
Solution Approach 1:
The clock shaping system dynamically adjusts the test clock signal parameters based on the operating state. During the second operating state (measurement mode), the system generates a test clock signal with a substantially fixed duty cycle but with adjustable rising or falling edges, enabling high-resolution timing measurement while maintaining operational simplicity through automated control.
Solution Approach 2:
The clock shaping system changes the timing parameters of the test clock signal based on the operating state. In the second operating state, the rising or falling edge of the test clock signal is selectively adjustable, allowing the system to capture state changes at high resolution within a single clock cycle while maintaining ease of operation through parameter-based control.
3Measurement precision
If multiple clock cycles are used for measurement, then accurate propagation time can be measured, but the measurement time and productivity are reduced
Solution Approach 1:
The initialization logic prepares the storage elements and measurement circuitry in advance by establishing the appropriate operating states before the actual measurement begins. This preliminary action ensures that when the test clock signal is applied, the system is ready to capture state changes immediately within a single clock cycle, eliminating the need for multiple cycles and significantly improving measurement productivity.
Solution Approach 2:
The measurement process is designed to complete the propagation time measurement within a single clock cycle by using the adjustable edge timing and initialization logic to rush through the measurement process. This skipping of multiple cycles maintains high measurement precision while dramatically improving productivity by completing measurements in one cycle rather than requiring multiple sequential measurements.
Data Source
AI summary
A test system in an integrated circuit includes a boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes initialization logic connected between an output of the first storage element and an input of the second storage element. The initialization logic provides the output of the first storage element to the input of the second storage element unchanged during a first operating state, and provides an inverted version of the output of the first storage element to the input of the second storage element during a second operating state. A bi-directional element is connected to receive an output of the second storage element, the bi-directional element feeding the output of the second storage element to an input of the first storage element, such that capture of a state change at the output of the first storage element at the output of the first storage element is facilitated during the second operating state.