Boundary Scan Controller with Independent Port Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Boundary scan technologies, compliant with IEEE 1149.x standards, face limitations in testing high-speed signals and large programmable devices due to low speed test platforms, which restrict the detection of manufacturing defects and programming efficiency, primarily due to constraints on the timing between Update and Capture events.
Innovation Solution
A testing system that allows independent control of the IEEE 1149.x clock signal's duty cycle, frequency, and phase shift across multiple ports, enabling time-shifted operation of boundary scan chains to decouple and realign Update and Capture events, thereby enhancing the ability to monitor propagation delays and improve programming speed without modifying the IEEE 1149.x standards or adding signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If boundary scan operations are performed according to IEEE 1149.x standards with fixed timing between Update and Capture events, then compliance with the standard is maintained, but the ability to test high-speed signals and detect manufacturing defects is limited
Solution Approach 1:
The patent introduces dynamic timing control by allowing the boundary scan controller to independently adjust the timing of Update and Capture events beyond the fixed 2.5 TCK cycle minimum. This enables the system to adapt timing parameters to match high-speed signal characteristics while maintaining standard compliance, thereby resolving the contradiction between standard adherence and test speed capability
Solution Approach 2:
The patent changes the timing parameters of boundary scan operations by allowing variable delays between Update and Capture events. By modifying these temporal parameters, the system can accommodate high-speed signals and large programmable devices while still operating within the IEEE 1149.x framework, thus improving productivity without sacrificing reliability
2Reliability
If the minimum time between Update and Capture events is maintained at 2.5 TCK cycles, then timing constraints are satisfied, but propagation delays occurring in less time cannot be observed accurately
Solution Approach 1:
The patent implements preliminary action by allowing Capture events to be triggered immediately after Update events complete, rather than waiting for the standard 2.5 TCK cycle minimum. This enables the system to capture propagation delays that occur in less time than the standard minimum interval, thereby improving measurement precision while maintaining timing constraint satisfaction through alternative synchronization methods
3Reliability
If boundary scan testing is performed at low speeds to maintain timing constraints, then standard compliance is achieved, but manufacturing defects cannot be detected
Solution Approach 1:
The patent applies dynamics by enabling the boundary scan system to operate at multiple speed levels. The controller can dynamically switch between low-speed mode for standard compliance and high-speed mode for defect detection, adapting the operating speed to the specific testing requirements while maintaining IEEE 1149.x compliance through proper timing management
4Adaptability or versatility
If multiple boundary scan devices are controlled with a single TCK frequency determined by the lowest operating device, then all devices can be controlled, but the maximum test speed is limited by the slowest device
Solution Approach 1:
The patent applies segmentation by dividing the multi-device boundary scan system into independent timing control domains. Each device can have its own adjustable timing parameters, allowing the controller to optimize the TCK frequency for each device individually while maintaining coordinated operation, thus overcoming the limitation imposed by the slowest device
Data Source
AI summary
A testing system including a plurality of ports, at least one controller, and a programmable memory. The plurality of ports may be adapted to implement an IEEE 1149.x standard interface. The at least one controller may be in electronic communication with at least one of the plurality of ports. The programmable memory may be in electrical communication with the at least one controller and adapted to store at least one clock forming variable. The at least one controller may be adapted to form an IEEE 1149.x clock signal for at least one of the plurality of ports based on the at least one clock forming variable. The at least one controller controls the IEEE 1149.x clock signal for at least one of the plurality of ports independently of the IEEE 1149.x clock signal for any other of the plurality of ports.