Boundary Scan Register Parallel Coupling for High-Frequency Connectivity Testing
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Solution Overview
Problem
Current JTAG standard is not adapted to test connectivity between devices communicating at high frequencies, limiting its effectiveness in modern integrated circuits with multiple communication paths.
Innovation Solution
A system and method utilizing parallel coupling of boundary scan registers between devices, with a tester controlling the writing and reading of test words at different frequencies to evaluate connectivity, enabling the determination of device connectivity by comparing the content of the target register with the test word.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If JTAG standard is used to test integrated circuits, then test access to internal components is enabled, but testing cannot be performed at high frequencies required by modern devices
Solution Approach 1:
The patent implements dynamic frequency scaling by allowing the boundary scan register to operate at different frequencies depending on the test mode. During normal JTAG operation, it uses standard low frequencies for serial shifting, but during parallel test mode, it dynamically switches to high frequencies to match modern device communication requirements, thus resolving the contradiction between maintaining JTAG compatibility and achieving high-speed testing
Solution Approach 2:
The patent segments the boundary scan register into multiple parallel lanes, allowing simultaneous data transfer across multiple paths. This segmentation enables the system to achieve high-frequency parallel testing while maintaining the original serial JTAG interface for compatibility, effectively separating the legacy interface function from the high-speed testing function
2Productivity
If parallel coupling of boundary scan registers is implemented, then high-frequency connectivity testing is enabled, but device complexity increases
Solution Approach 1:
The boundary scan register is designed to serve multiple functions: it operates as a traditional serial JTAG register for legacy compatibility, and simultaneously as a parallel high-speed test register for modern devices. This multi-functionality allows the same hardware structure to support both testing paradigms without requiring completely separate systems, thus improving productivity while limiting the increase in device complexity
Data Source
AI summary
A device and a method for testing a connectivity between a first device and a second device, the method includes: writing, at a first frequency and in a serial manner, a first test word to a source boundary scan register; writing a content of the source boundary scan register, at a second frequency and in a parallel manner, to a target boundary scan register; wherein the second frequency is higher than the first frequency; reading the content of the target boundary scan register; wherein the source and target boundary scan registers are selected from a first boundary scan register of the first device and a second boundary scan register of the second device; and evaluating a connectivity between the first and second device in response to a relationship between the first test word and the content of the target boundary scan register.