Boundary Scan Registers With Two-Phase Clock Control
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Solution Overview
Problem
Boundary scan registers face data racing issues due to clock skew and delay disparities between registers, which are difficult to match across varying temperatures and process conditions, especially in high-capacity chips with many I/O pins, leading to inefficiencies in testing and debugging.
Innovation Solution
A two-phase clock signal is generated using self-timed clock pulse generators for each boundary scan register, allowing data to be latched and output at specific edges of the clock cycle, ensuring that data is not transmitted prematurely, thus preventing data racing by maintaining synchronization across the register chain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single-phase clock signal is used to control boundary scan registers, then the device complexity is reduced, but data racing conditions occur due to clock skew and delay disparities between registers
Solution Approach 1:
The single-phase clock signal is segmented into two separate phases: a first phase signal and a second phase signal. Each phase is generated by dedicated pulse generators (first pulse generator and second pulse generator) that operate independently. This segmentation allows each register to receive clock signals at different times, preventing data racing conditions while maintaining manageable system complexity through modular architecture.
Solution Approach 2:
The patent implements periodic action by using sequential clock phases that cycle through different states. The first phase signal triggers data latching in one set of registers, while the second phase signal triggers latching in subsequent registers. This periodic sequencing ensures that data is transmitted through the register chain in a controlled, race-free manner while maintaining continuous operation.
2Reliability
If delay matching is implemented to compensate for clock skew, then data racing is prevented, but the manufacturing precision requirements increase and become difficult to maintain across temperature variations
Solution Approach 1:
The patent extracts the delay compensation function from the data path and relocates it to the clock generation path. Instead of trying to match delays in the data transmission path, the system generates clock signals with built-in time differences through separate pulse generators. This extraction eliminates the need for precise delay matching in the data path while achieving the same reliability goal.
Solution Approach 2:
The patent changes the timing parameters of the clock signals by introducing controlled delays between the first phase signal and the second phase signal. The pulse generators are configured to produce signals with specific time relationships that compensate for register-to-register delays. This parameter adjustment approach is more tolerant of manufacturing variations and temperature changes compared to fixed delay matching.
3Adaptability or versatility
If boundary scan registers are used in high-capacity chips with many I/O pins, then comprehensive testing capability is achieved, but timing race boundary issues become more pronounced and difficult to manage
Solution Approach 1:
The patent segments the clock control into multiple independent phase signals, each managed by dedicated pulse generators. This segmentation scales well with the number of registers, allowing each register in the high-capacity chip to be controlled independently without creating a single complex timing control path. The modular approach maintains versatility for comprehensive testing while managing complexity.
Solution Approach 2:
The patent introduces pulse generators as intermediary components between the clock source and the boundary scan registers. These intermediaries (first pulse generator and second pulse generator) handle the timing complexity by generating appropriately phased clock signals for each register. This intermediary layer isolates the timing race boundary issues from the test control logic, enabling comprehensive testing of high-capacity chips without proportionally increasing control complexity.
Data Source
AI summary
A chain of boundary scan registers is configured to use a two-phase clock signal to avoid data timing race conditions. The two-phase clock signal is generated according to a two-phase clock generator, which includes two self-timed clock pulse generators for each boundary scan register. The two-phase clock generator locally generates a self-timed clock pulse at the rising edge of a clock signal, which triggers a first stage of the boundary scan register. The two-phase clock generator also generates a self-timed clock pulse at the falling edge of the input clock signal, which triggers a second stage of the boundary scan register. The two-phase clock controlled boundary scan register includes two latches, each latch is triggered by one of the self-timed clock pulse generated locally from the rising and falling edge of the input clock signal.