Boundary Scan Test Driver and Receiver Circuit for Board Debugging
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Solution Overview
Problem
In large systems with many integrated circuits, debugging failures is challenging due to faults like solder overflow, pin shorts, and electro-static discharge, and the adoption of JTAG 1149.6 standard is slow due to the burden on IC designers with low-speed and high-speed pins co-existing, making in-system testing difficult.
Innovation Solution
A test driver transmitter circuit drives a test signal through a resistive termination circuit to a pin for boundary scan testing, and a test receiver receives the signal through a pass gate, allowing for loopback operations to test components without impacting data transmission performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If boundary scan testing is implemented in large systems with many integrated circuits, then defect detection capability is improved, but system complexity and debugging difficulty increase due to faults like solder overflow, pin shorts, and electro-static discharge
Solution Approach 1:
The system is segmented into multiple integrated circuits, each equipped with independent boundary scan cells that can autonomously perform testing functions. This segmentation allows distributed testing capability where each IC can be tested individually or in combination with others, reducing the overall system complexity by breaking down the testing function into manageable units.
Solution Approach 2:
Boundary scan cells serve as intermediary components inserted between the internal logic and external pins of integrated circuits. These intermediary cells provide controlled access to signal paths, enabling defect detection without requiring direct access to internal circuitry or complex external testing equipment, thus simplifying the overall testing system.
2Reliability
If JTAG 1149.6 standard is adopted for boundary scan testing, then testing coverage is improved, but design burden increases due to co-existing low-speed and high-speed pins
Solution Approach 1:
The boundary scan cells are designed with local quality differentiation, where each cell is configured according to the specific pin type (low-speed or high-speed) it is associated with. This allows the testing mechanism to adapt to different pin characteristics without requiring a completely different testing approach, reducing design burden while maintaining comprehensive testing coverage.
Solution Approach 2:
The boundary scan cells can change their operational parameters dynamically based on the pin type being tested. For high-speed pins, the cells operate with faster timing parameters, while for low-speed pins, they use slower timing parameters. This parameter adaptation allows a single standardized cell design to handle both pin types effectively, reducing design complexity.
3Measurement precision
If test signal transmission is performed through resistive termination circuits, then signal integrity is improved, but power consumption increases during data transmission
Solution Approach 1:
The resistive termination circuits are designed to be dynamically controllable, allowing the termination resistance to be adjusted or switched based on the current operational mode. During normal data transmission, the termination can be optimized for signal integrity, while during testing modes, different termination configurations can be applied. This dynamic control allows optimization of both signal integrity and power consumption under different operating conditions.
Data Source
AI summary
A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.