Boundary Scan Test Interface Circuit Reducing Horizontal Routes
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Solution Overview
Problem
The increasing number of horizontal routes between dynamic random access memory (DRAM) and printed circuit boards (PCBs) due to boundary scan tests on semiconductor memories leads to larger circuit sizes and higher costs.
Innovation Solution
A boundary scan test interface circuit with N test input pads and M test output pads, where M < N, utilizing logical gates such as XOR and XNOR gates, and inverters to reduce the number of horizontal routes by converting multiple input signals into fewer output signals, thereby reducing the number of signal lines needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If boundary scan test is processed on semiconductor memory with many address pins and control pins, then test coverage is improved, but the number of horizontal routes increases
Solution Approach 1:
The patent combines multiple test input pads (N pads) into fewer test output pads (M pads, where M < N) using logical gates. Multiple input signals are merged through XOR/XNOR gate operations to produce reduced number of output signals, thereby reducing the number of horizontal routes required while maintaining test coverage capability.
Solution Approach 2:
The patent changes the parameter of signal representation by using logical operations (XOR/XNOR) to transform multiple input signals into a reduced set of output signals. This parameter transformation allows the same test information to be conveyed through fewer signal lines, reducing horizontal route requirements.
2Reliability
If more horizontal routes are connected to address pins and control pins, then boundary scan test capability is improved, but circuit size is increased
Solution Approach 1:
The patent merges N test input pads into M test output pads (M < N) through logical gate operations, reducing the number of horizontal routes required. This merging reduces the circuit area occupied by interconnect routes while preserving the ability to perform comprehensive boundary scan tests on all address and control pins.
Solution Approach 2:
The patent introduces a logical operation dimension (XOR/XNOR gates) to process test signals, transforming the problem from one requiring direct one-to-one routing to one that uses computational processing to reduce signal lines. This dimensional change in signal processing allows fewer physical routes to carry equivalent test information.
3Reliability
If more horizontal routes are connected to address pins and control pins, then test coverage is improved, but prime cost is increased
Solution Approach 1:
The patent merges multiple test input pads into fewer output pads using logical gates, reducing the number of horizontal routes. This reduction directly decreases manufacturing complexity and prime cost, as fewer signal lines require fewer fabrication steps, less routing resources, and lower assembly costs, while maintaining full test coverage capability.
Data Source
AI summary
The invention provides a boundary scan test interface circuit. The boundary scan test interface circuit includes N test input pads, a test interfacing module and M test output pads, wherein N and M are positive integers, and M is smaller than N. The test interfacing module is coupled to the test input pads. The test interfacing module having a plurality of logical gates, and each of input pins of each of the logical gates coupled to each of the test input pads. The test output pads are coupled to output pins of the logical gates in the test interfacing module.