Boundary Sidewall Spacer for Embedded Memory Integrity
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Solution Overview
Problem
The formation of logic devices in integrated circuits with embedded memory technology and high k metal gate (HKMG) technology often results in damage to the boundary sidewall, leading to lateral undercutting, divots, and high k residue contamination, which can cause reliability issues and contamination of process tools.
Innovation Solution
A boundary sidewall spacer is formed to protect the dummy structure during the formation of logic devices, using a protecting dielectric layer that is removed concurrently with the pad layers, preventing undercutting and ensuring a smooth boundary sidewall free from high k residue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic devices are formed using conventional processes, then manufacturing productivity is maintained, but the boundary sidewall suffers damage including lateral undercutting, divots, and high k residue contamination
Solution Approach 1:
A boundary sidewall spacer is formed in advance before logic device fabrication to protect the boundary sidewall during subsequent processing steps. This preliminary protective structure prevents damage before it can occur, maintaining sidewall integrity throughout the logic device formation process without requiring additional time for repairs or rework.
Solution Approach 2:
The boundary sidewall spacer acts as an intermediary protective layer between the etch/resist processes and the boundary sidewall. This intermediate structure absorbs the harmful effects of lateral undercutting and prevents direct contact between contaminants and the boundary sidewall, thereby protecting it during high k metal gate processing.
2Reliability
If conventional fabrication processes are used, then manufacturing complexity is maintained, but high k residue contamination occurs on the boundary sidewall
Solution Approach 1:
The boundary sidewall spacer serves as a protective intermediary that prevents high k residue from directly contaminating the boundary sidewall during etch processes. This intermediate barrier structure allows conventional high k metal gate processes to proceed while preventing contamination, without requiring fundamental changes to the overall process architecture.
Solution Approach 2:
The harmful contamination effect is extracted and isolated from the boundary sidewall by introducing the spacer structure. The spacer takes on the role of being exposed to potential contaminants, thereby extracting the contamination risk away from the critical boundary sidewall region and protecting it from damage.
3Manufacturing precision
If the boundary sidewall is protected using additional structures, then manufacturing precision of the boundary sidewall is improved, but device complexity increases
Solution Approach 1:
The boundary sidewall spacer is formed as a preliminary protective structure before logic device fabrication begins. This pre-formed spacer provides a smooth template that prevents lateral undercutting and maintains boundary sidewall smoothness throughout subsequent processing, ensuring manufacturing precision without requiring complex in-process adjustments.
Solution Approach 2:
The protective spacer structure is applied locally only at the boundary region where sidewall protection is needed, rather than throughout the entire device structure. This localized approach maintains manufacturing precision at the critical boundary sidewall while minimizing the overall increase in device complexity.
Data Source
AI summary
Various embodiments of the present application are directed to a method of forming an integrated circuit (IC). An isolation structure is formed between a logic region and a memory region of a substrate. A dummy structure is formed on the isolation structure and defines a dummy sidewall of the dummy structure facing the logic region. A boundary sidewall spacer is formed covering the dummy structure and at least partially defines a boundary sidewall of the boundary sidewall spacer facing the logic region. A protecting dielectric layer is formed on a top surface of the boundary sidewall spacer by converting an uppermost portion of the boundary sidewall spacer to the protecting dielectric layer. The protecting dielectric layer is removed, and a logic device structure is formed on the logic region.