Boundary-Less Hierarchical Interconnects for FPGA Routing Efficiency
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Solution Overview
Problem
Existing FPGA circuitry faces inefficiencies in routing due to unevenly distributed interconnects and excessive unused routing tracks, which increase costs and decrease performance without providing benefits, as the number of routing tracks required varies significantly among designs with similar logic gate counts.
Innovation Solution
The development of boundary-less radix network architectures, where computing elements with M outputs and N inputs are connected through stages of switches, allowing each element to connect with others via one or more switches in multiple stages, and transforming radix-2 networks into boundary-less radix-3 networks by redistributing interconnect routing and pruning switches to achieve more efficient routing patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional hierarchical networks with fixed radix boundaries are used, then routing structure is simplified, but routing efficiency decreases and unused routing tracks increase
Solution Approach 1:
The patent implements dynamic routing by allowing routing tracks to span multiple hierarchy levels without being constrained by fixed radix boundaries. Routes can dynamically select whether to cross radix boundaries or traverse within the same hierarchy level based on destination requirements, making the routing structure adaptive rather than static.
Solution Approach 2:
The patent creates universal routing tracks that can serve multiple functions across different hierarchy levels. A single routing track can function both as a local interconnect within a radix group and as a long-distance interconnect spanning multiple radix boundaries, eliminating the need for dedicated tracks for each routing scenario.
2Adaptability or versatility
If adequate routing tracks are provided to accommodate all possible designs, then routing capacity is sufficient, but cost increases and performance decreases due to unused tracks
Solution Approach 1:
The patent implements dynamic routing by allowing routing tracks to span multiple hierarchy levels without being constrained by fixed radix boundaries. Routes can dynamically select whether to cross radix boundaries or traverse within the same hierarchy level based on destination requirements, making the routing structure adaptive rather than static.
Solution Approach 2:
The patent changes the fundamental parameter of routing track organization by eliminating fixed radix boundaries. Instead of having tracks confined to specific hierarchy levels, the system allows tracks to operate across multiple levels with variable scope, transforming the routing architecture from static to multi-scale dynamic.
3Quantity of substance
If routing tracks are minimized to match typical design requirements, then cost is reduced, but routing capacity becomes insufficient for designs with higher interconnect needs
Solution Approach 1:
The patent implements dynamic routing by allowing routing tracks to span multiple hierarchy levels without being constrained by fixed radix boundaries. Routes can dynamically select whether to cross radix boundaries or traverse within the same hierarchy level based on destination requirements, making the routing structure adaptive rather than static.
Solution Approach 2:
The patent ensures continuous routing capability across all hierarchy levels by eliminating boundaries that would interrupt routing paths. This allows routing tracks to maintain continuous useful action whether connecting adjacent logic blocks or spanning entire FPGA chips, maximizing the utilization of each track.
4Device complexity
If fixed radix boundaries are enforced in hierarchical networks, then network structure is regular and simple, but communication efficiency between elements across boundaries decreases
Solution Approach 1:
The patent implements dynamic routing by allowing routing tracks to span multiple hierarchy levels without being constrained by fixed radix boundaries. Routes can dynamically select whether to cross radix boundaries or traverse within the same hierarchy level based on destination requirements, making the routing structure adaptive rather than static.
Solution Approach 2:
The patent introduces asymmetry in routing track behavior across hierarchy levels. While the physical structure maintains hierarchical organization, the routing logic allows asymmetric treatment of boundary crossings versus intra-level routing, optimizing paths based on specific communication needs rather than enforcing uniform treatment.
Data Source
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AI summary
Systems and methods for implementing boundary-less hierarchical networks including methods of generating such networks in accordance with embodiments of the invention are disclosed. In one embodiment, a hierarchical network in an integrated circuit that includes a plurality of computing elements, where the plurality of computing elements have M outputs and N inputs, and a plurality of switches arranged into stages of switches wherein the plurality of computing elements are connected to switches in a first stage, the switches in the first stage are connected to the plurality of computing elements and switches in a second stage, where the switches in the second stage are connected to the switches in the first stage, at least M+1 adjacent computing elements can connect to at least two nearest neighboring computing elements via a stage 1 switch, and every computing element can connect with every other computing element within the hierarchical network.