Bounded Deadlock Check for Digital Circuit Verification
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Solution Overview
Problem
Verifying that a digital circuit design does not enter a deadlock or livelock state is challenging, especially with the increasing complexity of designs involving finite state machines, as existing methods require exhaustive simulations or are limited by computing resources when using liveness tools.
Innovation Solution
Employing safety tools for formal verification, which involve specifying a radius parameter to bound the distance between start and end states, and using fairness directives to exclude cycles with active wait signals, allowing for the efficient detection of locked states without exhaustive simulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exhaustive simulations are used to verify deadlock and livelock states, then verification completeness is improved, but computing time and resources increase significantly
Solution Approach 1:
The patent transforms the verification problem by changing parameters from unbounded state space exploration to bounded distance verification. By introducing a radius parameter that limits the maximum distance between start and end states, the method converts an exhaustive simulation approach into a bounded formal verification approach, significantly reducing computing time while maintaining verification effectiveness for locked state detection
Solution Approach 2:
The patent extracts and isolates the specific verification goal of detecting locked states (deadlock and livelock) from the broader state space verification problem. By focusing only on whether locked states exist within a bounded distance radius rather than verifying all possible state transitions, the method reduces computational complexity while maintaining reliability for the critical verification objective
2Difficulty of detecting and measuring
If liveness tools are used to detect locked states, then detection capability is improved, but device complexity and resource requirements increase
Solution Approach 1:
The patent segments the verification problem into multiple locked-state tests, each with a specific start state, end state, and radius parameter. This segmentation allows the complex liveness verification to be broken down into simpler bounded distance verification tasks, reducing the computational resources and tool complexity required while maintaining detection capability
Solution Approach 2:
The patent applies partial action by verifying only the necessary bounded distance properties rather than performing complete liveness verification. By checking whether locked states exist within a specified radius rather than exploring all possible infinite state transitions, the method reduces tool complexity and resource requirements while maintaining adequate detection capability
3Measurement precision
If fairness directives are used to exclude wait signal cycles, then verification accuracy is improved, but test complexity increases
Solution Approach 1:
The patent applies local quality by introducing fairness directives selectively for specific wait signals in particular locked-state tests. Rather than applying complex fairness constraints globally, the method selectively excludes cycles where specific wait signals are active only when needed for accurate locked state detection, maintaining verification accuracy while minimizing test complexity
Data Source
AI summary
An apparatus for verification of a digital circuit includes a memory and a processor. The memory is configured to store a model of at least part of the digital circuit and a list of one or more locked-state tests, each locked-state test including a start state, an end state and a radius parameter. The processor is configured to formally prove that for at least one of the locked-state tests, a maximum distance between the start state and the end state is bounded by a number that is not greater than the radius parameter, thereby verifying that the start state is not a locked state.