Bounded Liveness Verification Scalability via Counterexample Segmentation
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Solution Overview
Problem
Bounded liveness checking in logic design is inefficient due to the need for significant computational resources and the challenge of determining a minimal passing bound, often resulting in impractically large values that require extensive verification efforts, and the risk of verifying larger bounds than necessary, leading to computational resource degradation.
Innovation Solution
A method that analyzes and manipulates bounded liveness counterexamples to more likely exhibit counterexamples to deeper bounds, accelerating the falsification of liveness properties and quickly converging to a minimal passing bound by iteratively checking fewer irrelevant bounds, using algorithms like the Improved Bounded Livelock Synthesis Algorithm to optimize fairness and reduce computational requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bounded liveness verification is performed with larger bounds to ensure completeness, then verification thoroughness is improved, but computational resource consumption increases significantly
Solution Approach 1:
The patent segments the verification process into iterative phases, where each phase verifies a specific bound increment. Instead of verifying all bounds simultaneously, the method divides the verification into manageable segments that can be processed sequentially, reducing the computational burden on any single verification pass while maintaining overall thoroughness.
Solution Approach 2:
The patent performs preliminary analysis of counterexample traces to identify patterns and characteristics before conducting full verification. By analyzing the structure and properties of counterexamples in advance, the method can optimize the verification process and avoid unnecessary computational work on bounds that are unlikely to yield meaningful results.
2Reliability
If larger bounds are used in bounded liveness checking, then the completeness of verification is improved, but the time required for verification increases
Solution Approach 1:
The patent implements dynamic bound selection that adapts to the specific characteristics of the counterexample traces being analyzed. Rather than using fixed or uniformly increasing bounds, the method dynamically adjusts verification bounds based on observed patterns in the traces, allowing the verification process to focus computational effort on the most relevant bound ranges and skip unnecessary verification of larger bounds when patterns indicate futility.
Solution Approach 2:
The patent employs lightweight, disposable verification artifacts that can be quickly created and discarded. Counterexample traces are processed as temporary objects that are analyzed for patterns and then discarded, rather than being preserved for exhaustive verification. This approach allows rapid iteration through multiple bound values without the overhead of maintaining complex verification state across all bounds simultaneously.
3Measurement precision
If iterative verification is performed to find minimal passing bound, then precision of verification result is improved, but number of verification iterations increases
Solution Approach 1:
The patent implements feedback mechanisms that use results from each verification iteration to inform subsequent iterations. By analyzing verification outcomes and counterexample patterns from previous iterations, the method adjusts its approach for future iterations, avoiding redundant verification of the same bound ranges and converging more quickly to the minimal passing bound.
Solution Approach 2:
The patent changes verification parameters such as bound values and fairness constraints based on observations from previous iterations. Rather than systematically testing every possible bound value, the method adapts its parameter selection based on patterns observed in counterexamples, allowing it to skip over bound ranges that are unlikely to contain the minimal passing bound and focus on more promising regions.
Data Source
AI summary
A computer implemented method for increasing scalability in bounded liveness verification includes receiving, by one or more processors, a counterexample trace showing a bounded liveness failure and a set of parameters associated with the counterexample trace, partitioning the counterexample trace into segments representing bound increments contributing to the bounded liveness failure, selecting, by one or more processors, a time interval during which to repeat input values, wherein the selected time interval correlates to one or more segments, evaluating, by one or more processors, the received counterexample after repeating the selected time interval, determining, by one or more processors, whether the evaluation indicates that the counterexample falsifies a deeper bound with respect to a bound or an unbounded liveness counterexample, and, responsive to determining the evaluation indicates that the counterexample falsifies a deeper bound, providing, by one or more processors, counterexample falsification results.