Bowing-Shaped Through Silicon Via Adhesion
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Solution Overview
Problem
In semiconductor memory devices, through silicon vias with perpendicular side surfaces have low adhesion to the substrate, leading to potential dislodgment during assembly and solder connection due to applied loads, hindering the increase in memory capacity and operation speed.
Innovation Solution
The formation of via holes with a bowing shape, where the center portion has a larger diameter than the end portions, enhances the adhesion of through silicon vias by creating a bowing shaped portion and a notch, preventing them from falling out of the substrate during assembly and solder connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If through silicon vias are formed with perpendicular side surfaces, then the manufacturing process is simple, but the adhesion to substrate is low causing via dislodgment during assembly
Solution Approach 1:
The via hole side surface is formed with a bowing shape (curved surface) instead of a perpendicular shape. The curvature radius is specifically controlled to be 0.5-2.0 μm to optimize adhesion. This curved geometry increases the contact area between the via and substrate, preventing dislodgment during assembly while maintaining manufacturing feasibility through controlled etching processes.
2Quantity of substance
If memory chip capacity is increased by making each chip larger, then memory capacity increases, but yield rate decreases due to requirement for finer processing
Solution Approach 1:
The memory system is divided into multiple separate memory chips that are laminated together. Each chip maintains a manageable size with standard processing requirements, while the overall system achieves high memory capacity through vertical stacking. This segmentation allows each chip to be manufactured with conventional precision levels while the multi-chip architecture provides the desired total capacity.
3Adaptability or versatility
If front end unit is integrated into each memory chip, then interface function is provided, but operation speed is limited due to same manufacturing process as back end unit
Solution Approach 1:
The front end unit is separated from the memory chip and integrated into a dedicated interface chip. This allows the interface chip to use different manufacturing processes optimized for high-speed logic circuits, while memory chips focus on memory cell fabrication. The separation enables each component to be manufactured with process parameters optimized for its specific function, achieving both interface capability and high operation speed.
Data Source
AI summary
A semiconductor device includes a substrate including first and second surfaces, a first insulating film including third and fourth surfaces, the fourth surface being in contact with the first surface, and an electrode elongated to penetrate the substrate and the first insulating film, the electrode including a first portion and a second portion. The first portion includes first and second end parts and a center part sandwiched between the first and second end part. The first and second end parts of the first portion are smaller in diameter than at least a portion of the center part of the first portion. The second portion is located between the first portion and the third surface, and includes a third end part exposed from the third surface and a fourth end part connected to the first end part of the first portion.