Bowl-Shaped Interconnects for Misaligned 3D Memory Arrays

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Solution Overview

Problem

Existing 3D memory devices face issues with misalignment between stacked memory arrays, leading to decreased contact areas and increased contact resistance, which results in signal drop and performance deterioration.

Innovation Solution

Incorporation of bowl-shaped conductive structures between stacked memory arrays to ensure full contact between vertically extending conductive structures despite misalignment, using a metal material with a base portion and sidewalls to maintain electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional planar contact structures are used between stacked memory arrays, then manufacturing is simpler, but misalignment occurs leading to decreased contact area and increased contact resistance

Engineering Contradiction:
Improveelectrical contact reliabilityVSAvoidcontact structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies curvature by transitioning from planar contact surfaces to three-dimensional contact structures. Specifically, the lower contact structure includes a curved surface that conforms to the upper contact structure, and the upper contact structure includes a recessed portion that receives the lower contact structure. This curved interface ensures full contact between stacked memory arrays even when misalignment occurs, thereby maintaining electrical connectivity and reducing contact resistance.

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Reliability

If larger contact area is achieved through misalignment compensation, then contact resistance decreases, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecontact resistanceVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent implements beforehand cushioning by designing contact structures with inherent alignment tolerance. The lower contact structure includes a curved surface that extends beyond the upper contact structure's footprint, and the upper contact structure includes a recessed portion that accommodates the lower structure. This design creates a cushioning effect where misalignment is absorbed by the curved interface geometry rather than resulting in contact loss, thereby maintaining reliable electrical contact even when manufacturing alignment is not perfect.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If three-dimensional contact structures are implemented, then misalignment compensation is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvealignment toleranceVSAvoidcontact structure fabrication
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies segmentation by dividing the contact interface into distinct functional portions: the lower contact structure with its curved surface, the intermediate dielectric layer, and the upper contact structure with its recessed portion. This segmentation allows each component to be fabricated and optimized independently, with the curved surface and recessed portion being formed through separate patterning and deposition steps. This modular approach makes the complex three-dimensional contact structure more manageable and manufacturable compared to attempting to create the entire contact interface as a single monolithic structure.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250324586A1Semiconductor memory devices and methods of manufacturing thereof
Publication Date: 2025.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250324586A1 patent drawing
  • US20250324586A1 patent drawing
  • US20250324586A1 patent drawing

AI summary

A semiconductor device includes a first memory array which includes a first memory string including a plurality of first memory cells arranged in a vertical direction. The first memory array further includes a first conductive structure operatively coupled to the first memory string that extends through the first memory array in the vertical direction. The semiconductor device further includes a second memory array including a second memory string including a plurality of second memory cells arranged in the vertical direction. The second memory array further includes a second conductive structure operatively coupled to the second memory string that extends through the second memory array in the vertical direction. The semiconductor device further includes a bowl-shaped conductive structure interposed between the first and second memory arrays, and configured to operatively couple the first conductive structure to the second conductive structure.