Backpropagation Neural Network for IC Mask Optimization
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Solution Overview
Problem
Current mask optimization techniques for integrated circuits, such as inversion lithography technology, require hundreds of iterations and significant computational resources, leading to high time costs and heavy computation loads, especially for full-chip designs, which can take months to optimize.
Innovation Solution
The use of a backpropagation artificial neural network (ANN) model for pixel-based mask optimization, which selects layout regions, determines pixel images, and generates a full-chip pixel image, significantly reducing the number of iterations needed for optimization by using a BP ANN model that learns from input design layouts to produce optimized greyscale mask images.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional pixel-based mask optimization is applied to full-chip design layouts, then mask optimization accuracy is improved, but optimization time increases significantly (taking months)
Solution Approach 1:
The patent divides the full-chip design layout into multiple layout regions (e.g., first layout region, second layout region, etc.), processes each region independently through pixel-based mask optimization, and then combines the results. This segmentation reduces the computational complexity for each individual region, making the overall optimization process feasible within acceptable time frames while maintaining accuracy.
Solution Approach 2:
The patent performs preliminary actions by selecting and processing representative layout regions that capture the essential characteristics of the full-chip design. By optimizing these representative regions first and using them to train or guide the full-chip optimization, the system reduces the total optimization time while maintaining manufacturing precision.
2Manufacturing precision
If hundreds of optimization iterations are performed with OPC model simulation, then mask optimization accuracy is improved, but computation load becomes heavy
Solution Approach 1:
The patent segments the full-chip layout into multiple regions and performs optimization iterations on each region separately rather than simultaneously processing the entire chip. This reduces the computation load for each iteration step while maintaining the necessary accuracy through systematic processing of all regions.
Solution Approach 2:
The patent applies optimization to representative layout regions that may not cover the entire chip area, using these partial results to infer or guide the optimization of other regions. This partial action approach reduces the total computation load while achieving sufficient optimization accuracy for manufacturing purposes.
Data Source
AI summary
A method, a non-transitory computer-readable medium, and an apparatus for optimizing a design layout of an integrated circuit (IC) includes: selecting layout regions from a full-chip design layout for the IC; determining pixel images for the layout regions by performing pixel-based mask optimization for the layout regions, in which each pixel image corresponds to a respective layout region; determining a backpropagation (BP) artificial neural network (ANN) model using the pixel images and the layout regions; and determining a full-chip pixel image for the full-chip design layout using the BP ANN model, in which the BP ANN model uses the full-chip design layout as input.