B+ Tree Access Method Optimizing DRAM Utilization in All-Flash Arrays
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Solution Overview
Problem
The existing B+ tree structures in all-flash array storage systems face inefficiencies in read/write operations due to the high CPU overhead caused by frequent loading and unloading of data from Solid State Drives (SSDs) into Dynamic Random Access Memory (DRAM), which is costly and limited in capacity.
Innovation Solution
The proposed method optimizes B+ tree access by determining the availability of idle tree files in DRAM, creating new files if necessary, and strategically storing data across DRAM, DCPMM, and hard disk based on access frequency and layer thresholds, using Device Direct Access mode for DCPMM and setting dirty flags for periodic migration to maximize DRAM utilization and reduce CPU overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If B+ tree data is stored in SSD, then storage capacity is sufficient, but read/write speed is low due to long IO path
Solution Approach 1:
The patent segments B+ tree data into different storage locations based on access frequency: hot data (frequently accessed) is stored in DRAM, while cold data is stored in SSD. This segmentation allows frequent operations to occur in fast memory while maintaining overall storage capacity in SSD, directly resolving the speed versus capacity contradiction.
Solution Approach 2:
The patent introduces DCPMM (3D XPoint memory) as an intermediary storage layer between DRAM and SSD. This intermediary provides faster access than SSD while offering larger capacity than DRAM, serving as a buffer that reduces the IO path time for B+ tree operations without requiring all data to reside in expensive DRAM.
2Speed
If B+ tree data is frequently loaded into DRAM, then access speed improves, but CPU overhead increases due to frequent swapping
Solution Approach 1:
The patent implements dynamic data placement that adapts to access patterns. The system continuously monitors B+ tree node access frequency and dynamically migrates data between DRAM, DCPMM, and SSD based on current workload characteristics. This dynamic approach ensures that frequently accessed data resides in fast memory while reducing unnecessary swapping operations that would increase CPU overhead.
Solution Approach 2:
The patent employs feedback mechanisms through access frequency monitoring and dirty flag tracking. When B+ tree nodes are accessed, the system updates access statistics and uses this feedback to make intelligent decisions about data placement. The dirty flag mechanism provides feedback on which data needs to be written back, enabling efficient memory management that minimizes CPU overhead while maintaining fast access speeds.
3Productivity
If DRAM capacity is increased to store more B+ tree data, then access efficiency improves, but system cost increases due to expensive DRAM components
Solution Approach 1:
The patent applies local quality by providing different storage characteristics to different portions of B+ tree data based on their specific access requirements. Hot data that requires frequent access is placed in high-speed DRAM, while cold data is stored in lower-cost SSD. This localized optimization ensures that expensive DRAM resources are used only where they provide the most value, improving overall access efficiency without proportionally increasing DRAM capacity and cost.
Solution Approach 2:
The patent creates a composite storage system that combines multiple storage technologies (DRAM, DCPMM, and SSD) into a unified B+ tree storage solution. This composite approach leverages the strengths of each technology: DRAM provides fastest access for critical data, DCPMM provides intermediate speed and capacity, and SSD provides large capacity for less frequently accessed data. The result is a cost-effective system that achieves high access efficiency without requiring large amounts of expensive DRAM.
Data Source
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AI summary
Provided are a B+ tree access method and apparatus, and a medium. The method includes: when a B+ tree creation instruction is acquired, determining whether there is an idle underlying tree file mapped to a Dynamic Random Access Memory (DRAM); if YES, storing underlying data of a B+ tree in the underlying tree file; if NO, creating a new target underlying tree file, and mapping the target underlying tree file to the DRAM, so as to store the underlying data of the B+ tree in the target underlying tree file; and when a number of layers of the B+ tree is greater than or equal to a preset threshold, storing, in a preset storage area, data of a layer numbered to be greater than or equal to the preset threshold in the B+ tree. On the basis of a data structure of the B+ tree, data needs to be accessed from the underlying data whenever read. An underlying file is stored in the idle underlying tree file mapped to the DRAM, whereby the efficiency of accessing the underlying data is effectively improved. The other data is stored in a storage space other than the DRAM, whereby the utilization rate of DRAM resources is increased.