Buried Power Rail Layout With Enlarged Deep STI for nTSV Isolation
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Solution Overview
Problem
The integration of buried power rails in semiconductor substrates faces challenges due to critical dimension issues and poor overlay control, leading to potential shorting of nano through-silicon-vias with the substrate, which complicates the alignment and isolation of semiconductor devices.
Innovation Solution
A semiconductor structure is developed with a buried power rail (BPR) isolated by an enlarged deep shallow-trench-isolation (STI) region, and nano through-silicon-vias (nTSVs) are fully surrounded by this enlarged STI region to prevent shorting, achieved through the formation of enlarged deep STI regions and the use of dielectric materials to isolate the nTSVs from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the critical dimension of buried power rail is reduced to enable further scaling, then device integration density is improved, but manufacturing precision deteriorates leading to poor overlay control and potential shorting
Solution Approach 1:
An enlarged deep STI region is introduced as an intermediary structure between the substrate and the buried power rail. This mediator provides an additional isolation layer that compensates for overlay misalignment, preventing substrate shorting even when critical dimensions are reduced for scaling.
Solution Approach 2:
The enlarged deep STI region is formed beforehand to create a cushioning effect against potential shorting. By pre-establishing this enlarged isolation region, the design anticipates and prevents overlay errors that would otherwise cause substrate contact when the buried power rail dimensions are reduced.
2Device complexity
If the buried power rail is isolated by a standard STI region, then device complexity is reduced, but reliability deteriorates due to potential shorting between nTSV and substrate
Solution Approach 1:
The STI region is extended into the depth dimension to create an enlarged deep STI structure. By adding this vertical dimension to the isolation, the solution maintains relatively simple lateral geometry while achieving superior electrical isolation that prevents nTSV-to-substrate shorting.
3Reliability
If nano through-silicon via is formed to contact buried power rail, then electrical connectivity is improved, but manufacturing precision worsens due to alignment difficulty with small critical dimensions
Solution Approach 1:
The enlarged deep STI region serves as a mediator that decouples the alignment requirements between nTSV and buried power rail. By providing this intermediate isolation structure, the design allows greater alignment tolerance while maintaining reliable electrical connectivity through the nTSV contact.
Data Source
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AI summary
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a substrate layer; and a buried power rail (BPR) embedded in the substrate layer, wherein the BPR is isolated from the substrate layer by an enlarged deep shallow-trench-isolation (STI) region. In one embodiment, the enlarged deep STI region has a first width at near a top thereof and a second width at near a middle portion thereof, with the second width being larger than the first width. A method of making the above semiconductor structure is also provided.