Brain-like Computing Chip with Programmable Neuron Processors
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Solution Overview
Problem
Conventional brain-like chips lack programmability and computational efficiency due to limited support for various neuron models and lack of acceleration modules for multiplication and addition operations, leading to poor performance in simulating complex neural networks.
Innovation Solution
A brain-like computing chip with a many-core system featuring programmable neuron processors and parallel multiply-add-type coprocessors that perform energy integration operations, enabling efficient computation of various neuron models, including Spiking Neural Networks, through network-on-chip data transmission and shared memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional brain-like chips use ASIC implementation with one or two neuron models, then execution efficiency is high and power consumption is low, but programmability is poor and cannot support more models
Solution Approach 1:
The patent implements a universal neuromorphic processor that can support multiple neuron models (IF, LIF, Izhikevich, and custom models) through programmable parameters and configurations. The processor uses a unified architecture with configurable parameters (leakage coefficient, threshold, reset potential, etc.) that can be adjusted to simulate different neuron types, eliminating the need for separate ASIC implementations for each model while maintaining high execution efficiency.
2Adaptability or versatility
If programmable neuromorphic chips use many-core processors with general-purpose ARM processors, then programmability is improved, but computational efficiency is low due to lack of acceleration module for multiplication and addition
Solution Approach 1:
The patent segments the computation tasks by separating the control logic (handled by the ARM processor) from the computationally intensive multiply-accumulate operations (handled by dedicated MAC units). Each neuromorphic core contains specialized MAC circuits that are specifically optimized for neural network computations, allowing the general-purpose ARM processor to focus on control and coordination while the MAC units handle heavy mathematical operations in parallel.
Solution Approach 2:
The patent introduces an intermediate layer of specialized MAC (Multiply-Accumulate) units that act as mediators between the general-purpose ARM processors and the neuromorphic computation requirements. These MAC units provide accelerated computation for multiplication and addition operations, which are fundamental to neural network processing, thereby bridging the gap between programmability and computational efficiency.
3Device complexity
If brain-like chips lack acceleration module for multiplication and addition, then device complexity is low, but computational efficiency for neuron models requiring large computation is poor
Solution Approach 1:
The patent applies local quality by implementing specialized MAC (Multiply-Accumulate) units specifically within each neuromorphic core where they are most needed for neuron model computations. Rather than adding complex acceleration modules throughout the entire system, the patent locally enhances computational capability at the core level, providing efficient multiplication and addition operations exactly where neural network computations occur most frequently.
Data Source
AI summary
The present disclosure provides a brain-like computing chip and a computing device. The brain-like computing chip includes is a many-core system composed of one or more functional cores, and data transmission is performed between the functional cores by means of a network-on-chip. The functional core includes at least one neuron processor configured to compute various neuron models, and at least one coprocessor coupled to the neuron processor and configured to perform an integral operation and/or a multiply-add-type operation; and the neuron processor is capable of calling the coprocessor to perform the multiply-add-type operation.