Dual-Port BRAM Translation Look-Aside Buffer for Programmable Logic
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Solution Overview
Problem
Programmable integrated circuits (ICs) lack the capability to implement a translation look-aside buffer (TLB) due to the unavailability of content addressable memory (CAM), which is essential for efficient virtual address translation, especially when implementing soft processors within these circuits.
Innovation Solution
A dual-port block random access memory (BRAM) is used to create a TLB within a programmable IC, with two address ports and two data ports that concurrently search and output translation look-aside buffer data, allowing for efficient virtual address translation by utilizing direct mapped cache entries and TLB entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If content addressable memory (CAM) is used to implement TLB, then virtual address translation speed is improved, but device complexity and resource availability worsen due to unavailability of CAM in programmable ICs
Solution Approach 1:
The patent uses a copy of the virtual address stored in direct-mapped cache entries to enable comparison and translation lookup. Instead of using CAM to directly search for virtual addresses, the system creates and stores copies of virtual addresses in specific memory locations that can be compared using standard logic, thereby achieving translation functionality without requiring CAM hardware.
Solution Approach 2:
The patent introduces direct-mapped cache entries as an intermediary structure between the virtual address input and the TLB lookup process. These cache entries store copies of virtual addresses and serve as a mediator that enables the translation search to proceed through conventional memory access and comparison mechanisms rather than requiring direct CAM operation.
2Productivity
If dual-port BRAM is used to implement TLB, then resource usage efficiency is improved, but device complexity increases due to concurrent access requirements
Solution Approach 1:
The patent segments the BRAM into multiple sections (first section for direct-mapped cache entries, second section for TLB entries, third and fourth sections for additional TLB data) to enable independent concurrent access. Each section can be accessed simultaneously through different address ports without conflict, as the segmentation allows parallel operations on different memory regions.
Solution Approach 2:
The patent utilizes the dual-port capability of BRAM to access memory from two different dimensions simultaneously - one port for reading direct-mapped cache entries while another port reads TLB entries. This dimensional approach to memory access enables concurrent operations that would otherwise require sequential processing, improving resource efficiency.
Data Source
AI summary
A dual-port block random access memory (BRAM) can include first and second sections including direct mapped cache entries. The dual-port BRAM further can include third and fourth sections including translation look-aside buffer entries, wherein entries of the third section are associated with entries of the fourth section and wherein an entry of the third section and an associated entry of the fourth section collectively specify complete translation look-aside buffer data. The dual-port BRAM also can include first and second address ports concurrently accessing at least one of the first, second, third, or fourth sections of the dual-port BRAM to locate a virtual address to be translated.