Branch and Data Selector Nodes for FPGA Control Flow
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Solution Overview
Problem
Current programmable logic devices require extensive knowledge of hardware description languages like VHDL or Verilog for configuration, making it impractical for users without such expertise to efficiently program complex logic designs, especially with the need for long compile times that hinder development.
Innovation Solution
The use of high-level programming languages like OpenCL, which allows configuration of programmable devices through kernels and a host program, with precompiled virtual fabrics to reduce compilation time and facilitate control flow implementation, utilizing branch selector and data selector nodes to manage control signals and data flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If hardware description languages (VHDL/Verilog) are used for configuration, then device functionality can be implemented, but user accessibility and ease of programming deteriorate due to requiring specialized expertise
Solution Approach 1:
The patent introduces high-level programming languages (C, C++, Fortran, MATLAB) as an intermediary between the user and the hardware description languages. The translation system acts as a mediator that converts high-level code into VHDL/Verilog, allowing users without hardware description language expertise to program FPGAs effectively.
Solution Approach 2:
The patent replaces the manual process of writing hardware description languages with an automated translation system. Instead of users directly manipulating hardware description syntax, the system automatically translates high-level programming constructs into equivalent hardware description code, reducing the complexity barrier.
2Adaptability or versatility
If complex logic designs are implemented manually, then design flexibility is maintained, but compilation time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-compiling frequently used logic designs and storing them in a library. When users need these designs, the pre-compiled versions are directly applied without requiring full recompilation, significantly reducing compilation time while maintaining design flexibility through the ability to combine pre-compiled modules with custom code.
3Ease of operation
If translation from high-level languages to hardware description languages is performed, then user accessibility improves, but translation accuracy and reliability may deteriorate
Solution Approach 1:
The translation system incorporates feedback mechanisms including syntax validation, semantic analysis, and error reporting that provide users with information about translation issues. This allows users to verify and correct their high-level code before final compilation, ensuring translation accuracy while maintaining ease of use.
Data Source
AI summary
A method of configuring a programmable integrated circuit device to implement control flow at a current basic block. A branch selector node within the current basic block is configured to receive at least one control signal, where each of the at least one control signal is associated with a respective previous basic block. The branch selector node is further configured to select one of the at least one control signal based on one or more intended destinations for the at least one control signal, and provide the selected control signal to a data selector node within the current basic block. The data selector node is configured to select a data signal based on the selected control signal, where the selected data signal is from the respective previous basic block that is associated with the selected control signal.