Branch-destination buffer for reducing CPU branch penalty
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Solution Overview
Problem
Conventional microprocessor systems experience reduced processing performance due to branch penalty cycles when executing branch instructions, and existing solutions either increase circuit size and manufacturing cost or require larger instruction cache memory to enhance hit rates.
Innovation Solution
A memory control circuit with a branch-destination buffer, address comparison circuit, and buffer-update control circuit that caches branch-destination instructions and addresses, updating only when the instruction address changes in the negative direction, thereby reducing the number of accesses to memory during branch execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data capacity of the instruction cache memory is made larger to increase the hit rate during branch instruction execution, then the hit rate is improved, but the circuit size and manufacturing cost are increased
Solution Approach 1:
The patent segments the instruction cache memory into multiple sets (e.g., 4 sets of 4-way set associative cache), where each set handles specific address ranges. This segmentation allows the total cache capacity to be distributed across multiple smaller units, improving hit rate for branch instructions without requiring a single large cache that would increase overall circuit complexity.
Solution Approach 2:
The patent implements dynamic cache replacement policies and address mapping that adapt to branch instruction patterns. The cache system dynamically selects which instructions to retain based on access patterns, allowing efficient use of limited cache resources for branch-destination instructions while maintaining manageable circuit size.
2Reliability
If the data capacity of the instruction cache memory is made larger to increase the hit rate during branch instruction execution, then the hit rate is improved, but the manufacturing cost is increased
Solution Approach 1:
By dividing the cache into multiple smaller sets rather than implementing one large cache, the patent reduces manufacturing complexity and cost. Each set can be independently manufactured and tested, lowering overall production costs while maintaining high hit rates through the combined capacity of all sets.
Solution Approach 2:
The patent optimizes cache parameters such as associativity (4-way), number of sets (4), and block size to achieve the best balance between hit rate and manufacturing cost. These parameter adjustments allow the system to attain high branch instruction hit rates without requiring excessive cache capacity that would drive up manufacturing expenses.
3Reliability
If a counter is provided to count instruction cache accesses and initialize on subroutine calls or negative direction branches, then the hit rate during branch execution is improved, but the circuit size is increased
Solution Approach 1:
The patent merges the cache management functions with the existing instruction fetch pipeline and address generation logic. The cache controller integrates address comparison, tag matching, and data retrieval operations within the unified cache structure, eliminating the need for separate counter circuits and reducing overall device complexity while maintaining high branch hit rates.
Data Source
AI summary
A memory control circuit for providing a small-circuit-size memory control circuit capable of reducing a branch penalty during the execution of a branch instruction in a CPU. A branch-destination buffer caches a branch-destination instruction and a branch-destination-instruction address determined by a branch instruction executed by the CPU. When the CPU executes a branch instruction thereafter, if the branch-destination-instruction address output from the CPU matches an instruction address in the branch-destination buffer, the corresponding branch-destination instruction stored in the branch-destination buffer is sent to the CPU. When a branch instruction is executed, an address comparison circuit compares the branch-destination-instruction address with the branch-source-instruction address. A buffer-update control circuit updates data of the branch-destination buffer by the branch-destination instruction only when it is determined according to the result of comparison performed by the address comparison circuit that the instruction address has been changed in the negative direction by the instruction branch.