Branch-Future Instruction for Zero-Overhead Vector Loop Control

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Solution Overview

Problem

Branch instructions in data processing systems cause delays, reducing performance, as they require processing to branch from one sequence of instructions to another, leading to inefficiencies in processing pipelines.

Innovation Solution

The introduction of a branch-future instruction that includes programmable parameters for a branch target address and a predetermined instruction, allowing the processing circuitry to prepare for branching in advance, thereby reducing or eliminating delays by storing branch target and branch point data in a cache, enabling immediate branching when the predetermined instruction is reached.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If branch instructions are used to transition between instruction sequences, then program flow control is achieved, but processing delays occur reducing performance

Engineering Contradiction:

Improveprogram flow controlVSAvoidprocessing performance

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The patent introduces a branch-future instruction that allows the processing circuitry to prepare for branching in advance by specifying both a branch target address and a predetermined instruction. The system stores branch target data and branch point data in a cache before the actual branch is needed, enabling immediate transition when the predetermined instruction is reached, thus eliminating processing delays associated with traditional branch instructions

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If traditional branch instructions are used, then instruction sequence transition is possible, but processing overhead is introduced

Engineering Contradiction:

Improveinstruction sequence transitionVSAvoidprocessing overhead

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The branch-future instruction enables preliminary preparation of branch information including target address and branch point data, which are stored in cache memory in advance. When the predetermined instruction is executed, the branch has already been prepared, eliminating the time loss that would normally occur during branch execution

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces a cache memory structure that acts as an intermediary between the branch-future instruction and the actual branch execution. This cache stores both branch target data and branch point data, allowing the processing circuitry to quickly retrieve pre-prepared branch information without incurring traditional branch overhead

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS10768934B2Decoding predicated-loop instruction and suppressing processing in one or more vector processing lanes

Publication Date: 2020.09.08 ARM LTD

AI summary

A data processing system supports a predicated-loop instruction that controls vectorised execution of a program loop body in respect of a plurality of vector elements. When the number of elements to be processed is not a whole number multiple of the number of lanes of processing supported for that element size, then the predicated-loop instruction controls suppression of processing in one or more lanes not required.