Branch Conditional Instruction Dependency Skipping in Load-Compare-Jump Sequences
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Solution Overview
Problem
Conventional processor architectures face inefficiencies in processing 'load, compare, branch' instruction sequences due to dependencies that result in increased processing time and resource expenditure, especially as they handle higher instruction rates.
Innovation Solution
The proposed solution involves configuring the processor architecture to allow the branch conditional instruction to execute once the load instruction produces a result, skipping the need for the compare immediate instruction to finish, and utilizing a mapper to manage data dependencies, enabling auto-finishing of the compare immediate instruction when the branch conditional instruction is dispatched.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the branch conditional instruction waits for the compare immediate instruction to finish before executing, then the instruction dependencies are properly resolved, but the processing time increases and productivity decreases
Solution Approach 1:
The compare immediate instruction is auto-finished in advance by the finish logic unit before the branch conditional instruction executes. The finish logic unit proactively completes the compare instruction's finishing phase, preparing its results for subsequent use by the branch instruction, thereby eliminating the need for the branch instruction to wait for the compare instruction to finish.
Solution Approach 2:
The instruction execution process is segmented into distinct phases: dispatch, issue, execute, and finish. The patent applies different handling mechanisms to different phases - the execute phase maintains traditional dependency ordering while the finish phase is decoupled through auto-finishing, allowing parallel processing of finish operations without compromising execution correctness.
2Productivity
If the branch conditional instruction skips waiting for the compare immediate instruction to finish, then processing time is reduced and productivity improves, but the instruction dependency management becomes more complex
Solution Approach 1:
The finish logic unit acts as an intermediary between the compare immediate instruction and the branch conditional instruction. It receives the compare instruction, performs the auto-finish operation, and makes the results available to the branch instruction, thereby managing the dependency relationship without requiring the branch instruction to directly wait for or coordinate with the compare instruction's finish phase.
Solution Approach 2:
The compare immediate instruction's finish phase is serviced automatically by the finish logic unit without requiring active participation or waiting from the branch conditional instruction. The system self-manages the dependency resolution through automated finish tracking and result availability notification, reducing the complexity of inter-instruction coordination.
3Loss of time
If the compare immediate instruction is auto-finished when the branch conditional instruction is dispatched, then resource utilization improves and processing time is reduced, but the precision of instruction completion tracking must be maintained
Solution Approach 1:
The finish logic unit implements a feedback mechanism that tracks the completion status of instructions and notifies subsequent instructions when results are available. When the compare immediate instruction is auto-finished, the finish logic unit updates the status and provides feedback to the branch conditional instruction, ensuring accurate tracking of instruction completion without requiring the branch instruction to poll or wait actively.
Data Source
AI summary
A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.