Branch Merge Reduction for RLCM Circuit Timing Accuracy
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Solution Overview
Problem
As microcircuit devices become increasingly complex, designing and testing them becomes more challenging due to the need for precise timing verification, which requires compact circuit interconnect models that efficiently replicate the timing characteristics of the original circuit, while conventional methods face issues with accuracy and complexity.
Innovation Solution
The branch merge reduction technique merges branches of the original circuit network to reduce the number of nodes, creating a simpler realizable RCLM circuit that approximates the timing characteristics over a desired frequency range, using local circuit transformations and legitimacy criteria to ensure accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the original complex circuit network is used for timing verification, then the accuracy of timing characteristics is maintained, but the complexity of the circuit increases making design and testing more difficult
Solution Approach 1:
The patent merges branches of the original circuit network by eliminating nodes and combining their incident branches into a single branch. This merging process reduces the number of nodes and branches in the circuit model while maintaining the essential timing characteristics, thereby resolving the contradiction between accuracy and complexity.
Solution Approach 2:
The patent extracts and eliminates redundant nodes from the circuit network, keeping only the essential structure needed for timing verification. By removing unnecessary nodes and combining their functions into fewer branches, the circuit complexity is reduced while preserving the critical timing behavior.
2Device complexity
If model order reduction techniques are applied to reduce circuit complexity, then the circuit becomes simpler for analysis, but the accuracy of timing characteristics may be compromised
Solution Approach 1:
The branch merge operation combines multiple incident branches at a node into a single branch with equivalent electrical characteristics. This merging is performed in a way that preserves the timing characteristics of the original circuit, ensuring that the reduced circuit maintains accuracy while achieving complexity reduction.
Solution Approach 2:
The patent transforms the circuit network by changing its topological parameters (number of nodes and branches) through systematic node elimination and branch merging. This parameter transformation maintains the essential timing behavior while reducing the overall complexity of the circuit model.
3Measurement precision
If more nodes and branches are retained in the circuit model, then the timing characteristics are more accurately represented, but the time required for timing verification increases
Solution Approach 1:
By merging branches and eliminating nodes, the patent reduces the total number of elements in the circuit model that need to be analyzed during timing verification. This reduction directly decreases the computational time required for timing analysis while maintaining sufficient accuracy through the preservation of essential timing characteristics.
4Productivity
If the circuit network is reduced to fewer nodes and branches, then the analysis becomes more efficient, but the ability to accurately replicate original circuit behavior may be reduced
Solution Approach 1:
The branch merge operation combines multiple branches into a single equivalent branch that replicates the electrical behavior of the original set. This merging is designed to preserve the timing characteristics and overall behavior of the original circuit, ensuring that the reduced model remains reliable for analysis purposes.
Data Source
AI summary
Various tools and techniques are provided for reducing an original circuit network into a simpler, realizable RCLM circuit network. Branches of the original network are merged to reduce its total number of nodes. More particularly, the branches of the original circuit are merged so that the resulting reduced circuit approximately replicates the timing characteristics of the original circuit over the desired operating frequency range. The determination whether to merge two branches is made based upon one or more circuit characteristics associated with the node connecting the branches.